These sources introduce Voxel, a specialized simulation framework designed to evaluate the performance of 3D-stacked AI chips during large language model inference. This hardware architecture addresses memory bottlenecks by vertically integrating DRAM banks directly onto compute cores using high-density connectors. The research highlights that achieving peak efficiency requires a holistic hardware-software co-design, as performance depends heavily on how data and tasks are mapped across the distributed system. Findings indicate that optimized compute paradigms and intelligent tensor-to-bank placement can yield nearly twofold performance gains while significantly reducing memory conflicts. By open-sourcing the VoxelSim infrastructure, the authors provide a vital tool for exploring energy and thermal constraints in future AI hardware. Ultimately, the text argues that simple hardware scaling is insufficient without sophisticated compiler-aware execution strategies.