Episode 27 of The Quantum Computing Podcast with Fexingo gets inside the lab with a specific breakthrough: on May 7, 2026, a team at the University of Sydney published a paper demonstrating a real-time surface-code decoder implemented on an FPGA that runs at 1.2 microsecond latency — fast enough to keep up with current superconducting qubit readout cycles. Lucas and Luna break down what this means for the field: why error correction has lived in simulation for years, how this test in silicon actually changes the road to fault tolerance, and why a number like 1.2 microseconds matters more than a hundred logical qubits. They also discuss what the hardware hurdle looks like now — from cryogenic controllers to classical co-processors — and why 2026 may be remembered as the year error correction started moving from theory to testbed.

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