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Increasing EDA Performance & Throughput: Intel’s Latest Processors
Increasing Electronic Design Automation (EDA) performance and throughput is critical to Intel’s silicon Design engineers.
Silicon chip Design engineers at Intel face ongoing challenges: integrating more features into ever-shrinking silicon chips, bringing products to market faster and keeping Design engineering and manufacturing costs low. Design engineers run more than 273 million compute-intensive batch jobs every week. Each job takes from a few seconds to several days to complete.
As design complexity increases, so do the requirements for compute capacity, so refreshing servers and workstations with higher-performing systems is cost-effective and offers a competitive advantage by enabling faster chip design. Refreshing older servers also enables us to realize data center cost savings. By taking advantage of the performance and power-efficiency improvements in new server generations, we can increase computing capacity within the same data center footprint, helping to avoid expensive data center construction and reduce operational costs due to reduced power consumption.
To meet these engineers’ computing capacity requirements, Intel IT conducts ongoing throughput performance tests using real-world Intel silicon Design workloads. These tests measure EDA workload throughput and help us analyze the performance improvements—and in turn, business benefits offered by newer generations of Intel® processors.
We recently tested two-socket servers based on the Intel® Xeon® Platinum 8400 and Gold 6400 processor Series, operating single- and multi-threaded EDA applications running Intel silicon Design workloads for more than 113 hours (about 4 and a half days). Select results include the following:
• Higher frequency for per-core performance. For critical-path EDA workloads, selecting a high-frequency CPU like the Intel Xeon Gold 6444Y processor (32 cores per server) can deliver up to 1.14x higher per-core performance compared to lower-frequency, higher-core-count CPUs in the same generation of processors.
• Higher core counts for throughput. For volume validation runs, selecting a higher-core-count CPU at optimal frequency like the Intel Xeon Platinum 8462Y+ processor (64 cores per server) can deliver up to 1.75x higher Register Transfer Level (RTL) Simulation throughput per server when compared to a lower-core-count CPU (32 cores per server) in the same generation of processors. The Intel Xeon Platinum 8462Y+ processor (64 cores per server) completed workloads up to 2.17x faster than a previous-generation Intel Xeon Gold 6346 processor-based server, which has only 32 cores. Compared to a 2nd Gen Intel Xeon Gold 6246R processor (32 cores per server), the server with the newer processor outperformed the older processor by up to 2.40x in throughput.
Based on our performance assessment and our refresh cycle, we are deploying servers based on the 4th Gen Intel Xeon Scalable processor family in our data centers. By doing so, we have significantly increased EDA throughput performance to improve the overall EDA design cycles and optimize time to market of Intel® chips.
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By Intel
4.8
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Increasing Electronic Design Automation (EDA) performance and throughput is critical to Intel’s silicon Design engineers.
Silicon chip Design engineers at Intel face ongoing challenges: integrating more features into ever-shrinking silicon chips, bringing products to market faster and keeping Design engineering and manufacturing costs low. Design engineers run more than 273 million compute-intensive batch jobs every week. Each job takes from a few seconds to several days to complete.
As design complexity increases, so do the requirements for compute capacity, so refreshing servers and workstations with higher-performing systems is cost-effective and offers a competitive advantage by enabling faster chip design. Refreshing older servers also enables us to realize data center cost savings. By taking advantage of the performance and power-efficiency improvements in new server generations, we can increase computing capacity within the same data center footprint, helping to avoid expensive data center construction and reduce operational costs due to reduced power consumption.
To meet these engineers’ computing capacity requirements, Intel IT conducts ongoing throughput performance tests using real-world Intel silicon Design workloads. These tests measure EDA workload throughput and help us analyze the performance improvements—and in turn, business benefits offered by newer generations of Intel® processors.
We recently tested two-socket servers based on the Intel® Xeon® Platinum 8400 and Gold 6400 processor Series, operating single- and multi-threaded EDA applications running Intel silicon Design workloads for more than 113 hours (about 4 and a half days). Select results include the following:
• Higher frequency for per-core performance. For critical-path EDA workloads, selecting a high-frequency CPU like the Intel Xeon Gold 6444Y processor (32 cores per server) can deliver up to 1.14x higher per-core performance compared to lower-frequency, higher-core-count CPUs in the same generation of processors.
• Higher core counts for throughput. For volume validation runs, selecting a higher-core-count CPU at optimal frequency like the Intel Xeon Platinum 8462Y+ processor (64 cores per server) can deliver up to 1.75x higher Register Transfer Level (RTL) Simulation throughput per server when compared to a lower-core-count CPU (32 cores per server) in the same generation of processors. The Intel Xeon Platinum 8462Y+ processor (64 cores per server) completed workloads up to 2.17x faster than a previous-generation Intel Xeon Gold 6346 processor-based server, which has only 32 cores. Compared to a 2nd Gen Intel Xeon Gold 6246R processor (32 cores per server), the server with the newer processor outperformed the older processor by up to 2.40x in throughput.
Based on our performance assessment and our refresh cycle, we are deploying servers based on the 4th Gen Intel Xeon Scalable processor family in our data centers. By doing so, we have significantly increased EDA throughput performance to improve the overall EDA design cycles and optimize time to market of Intel® chips.