00:00? introduction

01:04? worked under Kunal Ghosh as an intern: https://www.vlsisystemdesign.com/basi...?

02:18? Questions from Niklas - time it takes, what's frustrating, fun?

05:40? Are the tools ready for mixed signal designs - DRC violations in Caravel.

07:20? Question from Pepijn - what would you need to change to alter the PLL?

08:44? PLL overview

10:00? Lakshmi's design: Frequency divider

12:22? Phase frequency detector

13:32? Charge pump

14:37? Voltage controlled oscillator

16:40? combined designs with Diego Hernando

17:10? putting into the Caravel wrapper, adding space

18:56? Question from Brady - why design an integrated loop filter

20:01? Questions from Top - are there schematics? Process corners and ngspice convergence

22:05? Question from Steven: post silicon testing

Lakshmi on Linked.in: https://www.linkedin.com/in/lakshmis96/?

Repo: https://github.com/lakshmi-sathi/avsd...