Welcome back, Michael Gielda of Antmicro!
Michael was on episode 519 talking about simulating embedded hardware using RenodeHe returned to talk about other projects that Antmicro is working on, especially those that are open source. The open source projects are indexed on the Antmicro Open Source Portal.Very niche stuff might be closed source, but people are surprised by what others might be interested in (if it were open sourced)Renode was the topic of our last interviewAI is a new target of open source work. Antmicro recently released the Kenning frameworkWhy another standard? Relevant XKCDTesting & benchmarking different AI models/frameworks across platforms from different vendors e.g. Nvidia, Modivius or Google CoralBlack boxes are bad for usersLLVM has hundreds of people looking at the projectCHIPS AllianceBrian Faith from QuickLogic,first ever FPGA vendor to adapt open source flowSammy Cheung from EfinixInterchange format for FPGA toolingVirtex Ultrascale PCIeWhat happens when a proprietary licensed company goes bankrupt?Renode is being used for pre-silicon SoC developmentCovered Renode-based CI’s in previous episodeOpen source toolchain stuffRISC-V: The ISA is common, but the cores are different.What is the center of gravity in the RISC V world? Many people are using SiFive.SiFive uses ChiselETH Zurich – another center of gravity - cores written in SystemVerilogPlace for diversityChisel (e.g. Antmicro's DMA core)SystemVerilog - enabling use of SystemVerilog code in open source toolsUVM – Universal Verification Methodology - recent progress with dynamic scheduling in VerilatorMigenZephyr bluetoothAbstraction as a response to chip shortageWhat if you wanted to do a fully open source flow? Let’s do a contrived security camera design example:Xilinx 7 series or Lattice ECP5 or Crosslink-NXOpen source HWhw board using the Nvidia Jetson, manufactured by past guest Chris OsterwoodVexRiscvLinux + LiteXLiteDRAMEthernet core – everything but the phyCo simulate with VerilatorRenodeEpisodes for open source toolchainTimClairePiotrCutting down on iterationChris mentions a past job that had 6 hour build cyclesAccelerating workflows using compute power and parallelizing dev processesWorking with GCP & building custom self-hosted GitHub runnersChip design using AI (Google)ScalenodeARVSOMBeagleVDC-SCM FPGA-based board management controllerOpen Compute ProjectRow HammerInterested in working with Antmicro? Get in touch!