The Amp Hour

Open Source Tapeout with Matthew Venn

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Welcome back to the show, Matthew Venn!

  • Matt was previously on Episode 467 from 2019 Supercon, before he started working on the open source toolchains and the education around them.
  • A bunch of news in the open source silicon space
    • Latest shuttle was MPW8, MPW9 coming up soon
    • 2 new open PDKs
    • Open source tools growing, much of it comes from Google "Willy Wonka-ing" process and sponsoring the shuttle
    • This was driven by past guest Tim Ansell (on 501)
    • Tim Edwards of efabless
    • Claire Wolf was on the show in the past
    • Dan Burke talked with Matt at Supercon 2023 about the term "Tapeout"
    • Matt runs the  ZeroToAsicCourse youtube channel, which includes a podcast.
    • Global Foundries / IHP open source
    • What is driving the growth?
      1. Open source tools
      2. Google MPW
      3. Open source PDK
      4. RISC V
      5. Ming Zhang on The Amp Hour talking about chiplets with ZGlue (now defunct).
      6. If you don't get into the lottery, you can pay efabless $10K for 300 chips
      7. Packaging is also tough
      8. Volume problems - What happens between 300 chips and 10K chips?
      9. Why should people get started with trying out the open source tools?
      10. Why are people signing up for the couse?
        • 30-50% want to understand silicon
        • 20% are academic -- many Universities are switching to the open source toolchain
        • 20-30% are commercial users who might want to use the info for
        • Reasons for going custom silicon as a business?
          • Security by obscurity
          • Space
          • Power
          • Sourcing (?)
          • MPW gives you about 10 sq mm
          • Matt put more designs onto his MPW slot, bundling even more designs (which has continued on)
          • OpenRAM
          • You could fit 25K of SRAM on 10 sq mm
          • #OpenSourceASICHighlight
          • Mohamed Kassem of eFabless was on the show in the past. eFabless highlights designs on their site.
          • Check out the 2022 highlight video from Matt!
          • Open Tapeout
          • FOSSI foundation runs the Latchup Conference
          • OSDA
          • India driving growth of chip design, many large scale companies also have verification teams in india
          • Security and "inspectability" from cloud companies
          • Root of trust chips - Laura from Oxide talked about this when she was on the show.
          • TSMC has an educational program for students in Taiwan
          • TinyTapeout
          • Extension of the course, joining designs together with a tristate bus
          • "Vosotros" is the "y'all" of the Spanish language
          • HDL is mostly controlled by the tools
          • OpenLane by eFabless was based on OpenRoad
          • TinyTapeout is meant for beginners
          • Uri from Wokwi (on show 599) worked with Matt on TinyTapeout
          • He added gates to Wokwi, which then can be connected together. The program pushes the gates out, which then can be synthesized.
          • You're closer to the hardware with Wokwi than you will be with Verilog.
          • 500-600 standard cells in tiny tapeout
          • The Shuttle lottery is getting harder to win
          • There are more TinyTapeout slots
          • It costs $25 for design only, $100 for chips
          • When you get the chip back on a PCB, you select your design (or others!) with a DIP switch
          • Check out what was on the TinyTapeout 2nd run
          • Olof Kindgren won the Serv RISC V prize, which is a small bit serial processor. Past guest Greg Davill put that design onto TinyTapeout.
          • There is a Discord for the course
          • Siliwiz explains how silicon can work, allows you to use sliders to control how the silicon gate sizes change.
          • A wafer will take 6 months start to finish if all goes well.
          • MPW1-4 had a hold violation. Sylvain (TNT) who was also on episode 467 did some wizardry to get things working!
          • Siliwiz still not open to public
          • What does it take to tape out a design? Putting the logic inside of other logic when creating a wafer. Then eFabless takes care of the rest.
          • The harness with everything that allows you to access the low level IO is called "caravel"
          • Europractice is another IC service
            • ...more
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