This episode explores the 1987 paper on synchronous data flow and how it turns stream-processing programs into analyzable graphs with fixed token production and consumption rates. It explains how those fixed rates let a compiler precompute a repeating execution schedule, prove steady-state consistency through balance equations, and allocate bounded buffers ahead of time instead of relying on expensive runtime scheduling. The discussion highlights why that tradeoff works so well for digital signal processing workloads like filtering, resampling, and codecs, while also showing why the model is too restrictive for messier software with irregular control flow. Listeners would find it interesting because it shows how a carefully limited programming model can unlock strong guarantees about performance, memory use, and parallel execution.

Sources:

1. Synchronous Data Flow for Signal Processing

https://ptolemy.berkeley.edu/publications/papers/87/synchdataflow/synchdataflow.pdf

2. Synchronous Data Flow — Edward A. Lee and David G. Messerschmitt, 1987

https://scholar.google.com/scholar?q=Synchronous+Data+Flow

3. Dataflow Process Networks — Edward A. Lee and Thomas M. Parks, 1995

https://scholar.google.com/scholar?q=Dataflow+Process+Networks

4. Cycle-Static Dataflow — Greet Bilsen, Marc Engels, Rudy Lauwereins, and Jean Peperstraete, 1996

https://scholar.google.com/scholar?q=Cycle-Static+Dataflow

5. Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing — Edward A. Lee and David G. Messerschmitt, 1987

https://scholar.google.com/scholar?q=Static+Scheduling+of+Synchronous+Data+Flow+Programs+for+Digital+Signal+Processing

6. Bounded Scheduling of Process Networks — Thomas M. Parks, 1995

https://scholar.google.com/scholar?q=Bounded+Scheduling+of+Process+Networks

7. Synthesis of Embedded Software from Synchronous Dataflow Specifications — Shuvra S. Bhattacharyya, Praveen K. Murthy, and Edward A. Lee, 1999

https://scholar.google.com/scholar?q=Synthesis+of+Embedded+Software+from+Synchronous+Dataflow+Specifications

8. StreamIt: A Language for Streaming Applications — William Thies, Michal Karczmarek, and Saman Amarasinghe, 2002

https://scholar.google.com/scholar?q=StreamIt%3A+A+Language+for+Streaming+Applications

9. Memory Management for Dataflow Programming of Multirate Signal Processing Algorithms — Shuvra S. Bhattacharyya and Edward A. Lee, 1994

https://scholar.google.com/scholar?q=Memory+Management+for+Dataflow+Programming+of+Multirate+Signal+Processing+Algorithms

10. Joint Minimization of Code and Data for Synchronous Dataflow Programs — Praveen K. Murthy, Shuvra S. Bhattacharyya, and Edward A. Lee, 1994

https://scholar.google.com/scholar?q=Joint+Minimization+of+Code+and+Data+for+Synchronous+Dataflow+Programs

11. Buffer Merging: A Powerful Technique for Reducing Memory Requirements of Synchronous Dataflow Specifications — Praveen K. Murthy and Shuvra S. Bhattacharyya, 2000

https://scholar.google.com/scholar?q=Buffer+Merging%3A+A+Powerful+Technique+for+Reducing+Memory+Requirements+of+Synchronous+Dataflow+Specifications

12. Pipeline Interleaved Programmable DSP's: Synchronous Data Flow Programming — Edward A. Lee and David G. Messerschmitt, 1987

https://scholar.google.com/scholar?q=Pipeline+Interleaved+Programmable+DSP%27s%3A+Synchronous+Data+Flow+Programming

13. Multirate Digital Filters, Filter Banks, Polyphase Networks, and Applications: A Tutorial — P. P. Vaidyanathan, 1990

https://scholar.google.com/scholar?q=Multirate+Digital+Filters%2C+Filter+Banks%2C+Polyphase+Networks%2C+and+Applications%3A+A+Tutorial

14. The Semantics of a Simple Language for Parallel Programming — Gilles Kahn, 1974

https://scholar.google.com/scholar?q=The+Semantics+of+a+Simple+Language+for+Parallel+Programming

15. First Version of a Data Flow Procedure Language — Jack B. Dennis, 1974

https://scholar.google.com/scholar?q=First+Version+of+a+Data+Flow+Procedure+Language

16. On the Boundedness of Process Networks — Gilles Kahn and David B. MacQueen, 1977

https://scholar.google.com/scholar?q=On+the+Boundedness+of+Process+Networks

17. Algorithm Design for Signal Processing — Charles S. Burrus, 1982

https://scholar.google.com/scholar?q=Algorithm+Design+for+Signal+Processing

18. DynVec: An End-to-End Framework for Efficient Vector-Dataflow Execution — approximate; recent systems/compiler authors, recent

https://scholar.google.com/scholar?q=DynVec%3A+An+End-to-End+Framework+for+Efficient+Vector-Dataflow+Execution

19. Compiler discovered dynamic scheduling of irregular code in high-level synthesis — approximate; recent HLS/compiler authors, recent

https://scholar.google.com/scholar?q=Compiler+discovered+dynamic+scheduling+of+irregular+code+in+high-level+synthesis

20. Dataflow Models of computation for programming heterogeneous multicores — approximate; recent embedded/parallel-systems authors, recent

https://scholar.google.com/scholar?q=Dataflow+Models+of+computation+for+programming+heterogeneous+multicores

21. Heuristic & Expert-Guided Buffer Sizing for Neural Network Inference Applications on FPGAs — approximate; recent FPGA/dataflow authors, recent

https://scholar.google.com/scholar?q=Heuristic+%26+Expert-Guided+Buffer+Sizing+for+Neural+Network+Inference+Applications+on+FPGAs

22. Sgcn: Exploiting compressed-sparse features in deep graph convolutional network accelerators — approximate; recent accelerator authors, recent

https://scholar.google.com/scholar?q=Sgcn%3A+Exploiting+compressed-sparse+features+in+deep+graph+convolutional+network+accelerators

23. Safe shared state in dataflow systems — approximate; recent programming-systems authors, recent

https://scholar.google.com/scholar?q=Safe+shared+state+in+dataflow+systems

24. An Intermediate Representation for Stateful Dataflows — approximate; recent systems authors, recent

https://scholar.google.com/scholar?q=An+Intermediate+Representation+for+Stateful+Dataflows

25. AI Post Transformers: FlatAttention for Tile-Based Accelerator Inference — Hal Turing & Dr. Ada Shannon, 2026

https://podcast.do-not-panic.com/episodes/2026-04-04-flatattention-for-tile-based-accelerator-56e6ca.mp3

26. AI Post Transformers: Caffeine: A Unified FPGA for CNNs — Hal Turing & Dr. Ada Shannon, 2026

https://podcast.do-not-panic.com/episodes/2026-05-06-caffeine-a-unified-fpga-for-cnns-e8acbe.mp3

27. AI Post Transformers: Caffe and the Rise of CNN Frameworks — Hal Turing & Dr. Ada Shannon, 2026

https://podcast.do-not-panic.com/episodes/2026-05-06-caffe-and-the-rise-of-cnn-frameworks-cf15f3.mp3

Interactive Visualization: Synchronous Data Flow for Signal Processing