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[014] Industry briefing - EUV The Focal Point
This week’s EUV conversation is about signals, not shipments: Intel ties its 18A node to a mainstream CES launch, ASML swats away a cybersecurity rumor, and imec frames 2026 as a race to compress learning cycles. With TSMC in a quiet period ahead of earnings, the industry is temporarily trading on inference — and that makes EUV capacity and High-NA readiness the real subtext.
Key takeaways:
- Intel positioned Panther Lake / Core Ultra Series 3 as a broadly adopted AI PC platform built on 18A, a test of high-volume manufacturing maturity.
- CEO messaging around “going big time into 14A” signals continued node ambition and keeps EUV ecosystem planning active.
- ASML said social-media claims of a data breach were untrue, underscoring the security perimeter around strategic lithography infrastructure.
- No major new EUV scanner shipment announcements surfaced in the last several days.
- TSMC’s quiet period ahead of its January 15 earnings call limits near-term public roadmap detail, so some demand signals remain indirect.
- Imec’s 2026 strategy emphasizes XTCO, explicitly linking EUV progress to faster end-to-end learning across compute, memory, packaging, and interconnect.
- Imec says a next-generation High-NA scanner is set to be installed in Leuven in 2026, expanding the ecosystem’s real-wafer learning capacity.
- In 2026, “speed” in EUV increasingly means learning per quarter, not just wafers per hour.
Glossary:
EUV — Extreme ultraviolet lithography using ~13.5 nm wavelength light for leading-edge patterning.
High-NA — High numerical aperture EUV optics enabling tighter imaging for smaller pitches.
18A — Intel process node branding associated with a leading-edge manufacturing generation.
XTCO — Cross-technology co-optimization; jointly optimizing device, interconnect, packaging, power, and thermals.
Edge placement error — Combined pattern placement uncertainty that drives yield and performance at small geometries.
Stochastic defects — Random, shot-noise-driven patterning failures that become more visible at extreme pitches.
Overlay — Alignment accuracy between successive lithography layers.
OPC — Optical proximity correction; computational pattern adjustments to print intended shapes on wafer.
Pellicle — Thin membrane protecting EUV masks from particles while withstanding high-power exposure.
This podcast was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.
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By EUV The Focal Point - TeamThis week’s EUV conversation is about signals, not shipments: Intel ties its 18A node to a mainstream CES launch, ASML swats away a cybersecurity rumor, and imec frames 2026 as a race to compress learning cycles. With TSMC in a quiet period ahead of earnings, the industry is temporarily trading on inference — and that makes EUV capacity and High-NA readiness the real subtext.
Key takeaways:
- Intel positioned Panther Lake / Core Ultra Series 3 as a broadly adopted AI PC platform built on 18A, a test of high-volume manufacturing maturity.
- CEO messaging around “going big time into 14A” signals continued node ambition and keeps EUV ecosystem planning active.
- ASML said social-media claims of a data breach were untrue, underscoring the security perimeter around strategic lithography infrastructure.
- No major new EUV scanner shipment announcements surfaced in the last several days.
- TSMC’s quiet period ahead of its January 15 earnings call limits near-term public roadmap detail, so some demand signals remain indirect.
- Imec’s 2026 strategy emphasizes XTCO, explicitly linking EUV progress to faster end-to-end learning across compute, memory, packaging, and interconnect.
- Imec says a next-generation High-NA scanner is set to be installed in Leuven in 2026, expanding the ecosystem’s real-wafer learning capacity.
- In 2026, “speed” in EUV increasingly means learning per quarter, not just wafers per hour.
Glossary:
EUV — Extreme ultraviolet lithography using ~13.5 nm wavelength light for leading-edge patterning.
High-NA — High numerical aperture EUV optics enabling tighter imaging for smaller pitches.
18A — Intel process node branding associated with a leading-edge manufacturing generation.
XTCO — Cross-technology co-optimization; jointly optimizing device, interconnect, packaging, power, and thermals.
Edge placement error — Combined pattern placement uncertainty that drives yield and performance at small geometries.
Stochastic defects — Random, shot-noise-driven patterning failures that become more visible at extreme pitches.
Overlay — Alignment accuracy between successive lithography layers.
OPC — Optical proximity correction; computational pattern adjustments to print intended shapes on wafer.
Pellicle — Thin membrane protecting EUV masks from particles while withstanding high-power exposure.
This podcast was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.