"3 nanometer." "2 nanometer." "18A." These labels sound like simple size numbers, but they are really product-family names that bundle transistor architecture, power delivery, design rules, and manufacturing maturity. This episode explains what a node actually means in the EUV era, why Intel/TSMC/Samsung nodes do not line up, and how economics pushes modern chips toward variants, chiplets, and advanced packaging.

Key Takeaways

- A node name is a brand, not a ruler; the nanometer label is not a single physical dimension.

- Comparing nodes across companies by name alone is misleading; compare deliverables like transistor type, power delivery, and ramp maturity.

- TSMC positions N2 as its first nanosheet (gate-all-around) node with volume production starting in late 2025, and A16 adds a backside-power concept (SPR).

- Samsung's SF3 is a GAA-plus-EUV node, and Samsung has published a staged SF2 ramp plan (mobile first, then HPC and automotive).

- Intel 4 is Intel's first production node using EUV, and Intel 18A pairs RibbonFET (GAA) with PowerVia (backside power) with a stated HVM target in 2H 2025.

- DRAM "nodes" (1z, 1-alpha, 1-beta, 1-gamma, 1anm) are ten-nanometer-class generations, not comparable to logic nanometer labels; EUV is added selectively and increasingly.

- NAND scaling is primarily about vertical layer count; more layers raise etch and yield complexity but improve bits per wafer.

- EUV and High-NA EUV economics matter: tool cost, fab energy demand, and yield risk shape which products move first and why chiplets and packaging keep growing.

Glossary

- Node: A manufacturing generation name for a platform (rules, devices, interconnect, libraries, maturity), not a literal feature size.

- PPA: Power, performance, area - shorthand foundries use to summarize expected node improvements.

- FinFET: A transistor with a fin-shaped channel and a gate that wraps around multiple sides.

- Gate-all-around (GAA): A transistor where the gate surrounds the channel more completely (often implemented as nanosheets/nanoribbons).

- Nanosheet / nanoribbon: A GAA device shape using stacked thin channels to improve electrostatic control.

- Backside power delivery: Routing power from the back of the wafer to reduce front-side routing congestion and improve power integrity.

- EUV: Extreme ultraviolet lithography; used to pattern very small features, but it is capital- and energy-intensive.

- HVM: High-volume manufacturing; the phase when a node is producing at scale with stable yields.

- DRAM: Dynamic random-access memory; scaling is constrained by the repeating cell and capacitor/access-device integration.

- NAND: Non-volatile flash memory; scaling is largely vertical (more layers) and limited by deep etch, deposition, and yield.

This week’s EUV conversation is about signals, not shipments: Intel ties its 18A node to a mainstream CES launch, ASML swats away a cybersecurity rumor, and imec frames 2026 as a race to compress learning cycles. With TSMC in a quiet period ahead of earnings, the industry is temporarily trading on inference — and that makes EUV capacity and High-NA readiness the real subtext.

Key takeaways:

- Intel positioned Panther Lake / Core Ultra Series 3 as a broadly adopted AI PC platform built on 18A, a test of high-volume manufacturing maturity.

- CEO messaging around “going big time into 14A” signals continued node ambition and keeps EUV ecosystem planning active.

- ASML said social-media claims of a data breach were untrue, underscoring the security perimeter around strategic lithography infrastructure.

- No major new EUV scanner shipment announcements surfaced in the last several days.

- TSMC’s quiet period ahead of its January 15 earnings call limits near-term public roadmap detail, so some demand signals remain indirect.

- Imec’s 2026 strategy emphasizes XTCO, explicitly linking EUV progress to faster end-to-end learning across compute, memory, packaging, and interconnect.

- Imec says a next-generation High-NA scanner is set to be installed in Leuven in 2026, expanding the ecosystem’s real-wafer learning capacity.

- In 2026, “speed” in EUV increasingly means learning per quarter, not just wafers per hour.

Glossary:

EUV — Extreme ultraviolet lithography using ~13.5 nm wavelength light for leading-edge patterning.

High-NA — High numerical aperture EUV optics enabling tighter imaging for smaller pitches.

18A — Intel process node branding associated with a leading-edge manufacturing generation.

XTCO — Cross-technology co-optimization; jointly optimizing device, interconnect, packaging, power, and thermals.

Edge placement error — Combined pattern placement uncertainty that drives yield and performance at small geometries.

Stochastic defects — Random, shot-noise-driven patterning failures that become more visible at extreme pitches.

Overlay — Alignment accuracy between successive lithography layers.

OPC — Optical proximity correction; computational pattern adjustments to print intended shapes on wafer.

Pellicle — Thin membrane protecting EUV masks from particles while withstanding high-power exposure.

This podcast was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

Transistors are the “switches” inside every modern processor, but they aren’t just tiny on/off buttons. In this episode, we build an intuition for how MOSFET transistors work, and why EUV lithography matters even though it doesn’t change the transistor’s basic physics. We then take a quick tour of the leading-edge shift from FinFETs to gate-all-around nanosheet devices, plus what’s coming next.

Key takeaways

- A MOSFET controls current by using a gate electric field to create or remove a thin conductive channel between source and drain.

- “Off” is never perfectly off: subthreshold leakage is fundamental and becomes harder to suppress as devices shrink.

- Performance and energy are increasingly limited by capacitances, contact resistance, and interconnect, not just the channel itself.

- EUV lithography uses 13.5 nm light, reflective optics, and vacuum, enabling tight patterning for advanced nodes.

- EUV introduces stochastic variability (randomness) that shows up as roughness and occasional pattern failures at tiny dimensions.

- FinFETs wrap the gate on three sides of a fin for better control than planar transistors.

- Gate-all-around nanosheet transistors wrap the gate fully around the channel, improving electrostatics and offering flexible drive strength.

- The leading edge is converging on GAA plus improved power delivery (including backside concepts) plus more advanced EUV tools (High-NA) where it makes sense.

Glossary

- Transistor: A device that controls current flow; in logic chips it functions as a switch.

- MOSFET: A transistor where a gate electric field modulates a channel through an insulating dielectric.

- Gate / Source / Drain: The control terminal (gate) and the two terminals between which current flows (source and drain).

- Channel (inversion layer): The thin conductive region created under the gate that allows current to flow.

- FinFET: A 3D MOSFET where the gate wraps around a silicon fin on three sides to improve control.

- GAA / nanosheet: Gate-all-around transistor where the gate surrounds thin silicon sheets that form the channel.

- EUV lithography: Patterning with 13.5 nm light using reflective optics in vacuum to print very small features.

- High-NA EUV: A newer EUV generation with higher numerical aperture (0.55) for better resolution and contrast.

- Backside power delivery: Routing power on the wafer backside to reduce congestion and power drop in front-side wiring.

This article was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

EUV The Focal Point delivers updates on the global semiconductor industry. The podcast explains key developments in EUV and (High-)NA lithography, leading-edge logic nodes, DRAM and HBM. It follows the strategies of ASML, Intel, TSMC, Samsung, SK Hynix, Micron and Rapidus. Clear, concise and accessible. For everyone who wants to understand how advanced chips are built and why they shape the global economy.

This podcast was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

EUV The Focal Point delivers updates on the global semiconductor industry. The podcast explains key developments in EUV and (High-)NA lithography, leading-edge logic nodes, DRAM and HBM. It follows the strategies of ASML, Intel, TSMC, Samsung, SK Hynix, Micron and Rapidus. Clear, concise and accessible. For everyone who wants to understand how advanced chips are built and why they shape the global economy.

This podcast was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

EUV The Focal Point delivers updates on the global semiconductor industry. The podcast explains key developments in EUV and (High-)NA lithography, leading-edge logic nodes, DRAM and HBM. It follows the strategies of ASML, Intel, TSMC, Samsung, SK Hynix, Micron and Rapidus. Clear, concise and accessible. For everyone who wants to understand how advanced chips are built and why they shape the global economy.

This podcast was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

The Integrated Circuit (IC), also known as a microchip or simply chip, is a compact assembly of electronic circuits—such as transistors, resistors, and capacitors—and their interconnections, fabricated onto a thin, flat piece of semiconductor material, most commonly silicon. Compared to assemblies built from discrete components, ICs are orders of magnitude smaller, faster, more energy-efficient, and less expensive, and have revolutionized modern technology. The development began in 1958 with Jack Kilby, who successfully demonstrated the first working example. Robert Noyce developed the first practical monolithic silicon IC chip in 1959. Modern chips utilize Very-Large-Scale Integration (VLSI) and may contain billions of transistors.

This article was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

EUV The Focal Point delivers updates on the global semiconductor industry. The podcast explains key developments in EUV and (High-)NA lithography, leading-edge logic nodes, DRAM and HBM. It follows the strategies of ASML, Intel, TSMC, Samsung, SK Hynix, Micron and Rapidus. Clear, concise and accessible. For everyone who wants to understand how advanced chips are built and why they shape the global economy.

This podcast was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

The CO2 laser, invented in 1964, is one of the most useful and highest-power continuous-wave gas lasers currently available, emitting in the infrared region (wavelengths centering on 9.6 and 10.6 micrometers (μm)). Traditionally, it is used in industrial applications for cutting, welding, and engraving, as well as in surgery for soft-tissue procedures.

Currently, the CO2 laser plays a decisive role in EUV lithography for manufacturing the latest generation of microchips. The TRUMPF Laser Amplifier is a pulsed CO2 laser system that strikes 50,000 tin droplets per second inside a vacuum chamber. This process creates an intensive plasma, which emits Extreme Ultraviolet (EUV) radiation with an optimal wavelength of 13.5 nanometers.

Components such as the High Power Seed Module (HPSM) are essential for optimally shaping the pulses and ensuring the commercial viability of EUV technology.

ASML recently honored TRUMPF for a new EUV high-energy laser that is scheduled for series production starting in 2026. This laser is intended to increase the availability and power of the EUV products while contributing to lower energy consumption.

This article was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

EUV The Focal Point delivers updates on the global semiconductor industry. The podcast explains key developments in EUV and (High-)NA lithography, leading-edge logic nodes, DRAM and HBM. It follows the strategies of ASML, Intel, TSMC, Samsung, SK Hynix, Micron and Rapidus. Clear, concise and accessible. For everyone who wants to understand how advanced chips are built and why they shape the global economy.

This podcast was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.