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This week’s episode looks at how EUV demand is turning into explicit capital commitments instead of general roadmap talk. The headline items are SK hynix’s nearly $8 billion scanner order, imec’s High-NA EUV installation in Leuven, and the way AI memory and foundry partnerships are starting to reshape lithography demand. The bigger point is that the scarce resource is no longer just the machine. It is early access to the whole learning curve around the machine.

Key takeaways

- SK hynix disclosed a 11.95 trillion won purchase of EUV scanners from ASML Korea, with completion scheduled by December 31, 2027.

- imec received an ASML EXE:5200 High-NA EUV system in Leuven and expects full qualification by Q4 2026.

- The imec tool will support the NanoIC pilot line and gives ecosystem partners shared access to early High-NA process learning.

- Samsung and AMD said they will align on primary HBM4 supply for AMD’s Instinct MI455X and also discuss a future foundry partnership.

- Micron raised fiscal 2026 capital spending plans by $5 billion to more than $25 billion, with more increases expected in 2027.

- Micron has started retrofitting the Tongluo P5 site in Taiwan, plans a second cleanroom there by the end of fiscal 2026, and expects meaningful shipments from the existing fab in fiscal 2028.

- Broadcom said TSMC capacity is becoming a bottleneck into 2027, reinforcing the case for earlier capacity reservation across the AI supply chain.

- Europe’s EUV leverage remains system-level: scanner integration, optics, source technology, and shared pilot-line process development.

Glossary

Extreme Ultraviolet (EUV) lithography — Chip patterning technology that uses 13.5-nanometer light to print very small features.

High Numerical Aperture (High-NA) EUV — The next EUV generation with higher optical numerical aperture for tighter patterning and fewer multi-patterning steps.

EXE:5200 — ASML’s High-NA EUV platform now being installed at selected early-access sites.

High Bandwidth Memory 4 (HBM4) — A stacked memory generation designed for AI accelerators that need very high bandwidth and power efficiency.

Pilot line — A shared development environment used to validate processes, materials, and integration before high-volume production.

Cost per wafer — The effective manufacturing cost of processing one wafer, influenced by tool throughput, uptime, yield, and process complexity.

Overlay — The accuracy with which one lithography layer is aligned to previous layers on the wafer.

Laser-produced plasma (LPP) source — The EUV light source method in which lasers hit tin droplets to generate 13.5-nanometer radiation.

This article was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

EUV lithography isn’t just a machine purchase. It’s an ecosystem-scale coordination problem with a balance sheet attached. This episode explains “coordinated manufacturability” in EUV terms: how chipmakers line up design, masks, materials, metrology, facilities, software, and service so that a quarter‑billion‑dollar bottleneck actually produces shippable chips.

KEY TAKEAWAYS

- EUV economics are dominated by fixed costs. The payback comes from sustained utilization, yield, and fast learning cycles.

- A modern EUV scanner is priced in the hundreds of millions of dollars, and High‑NA tools are around $400 million each.

- The “EUV bill” includes far more than scanners: masks, inspection, materials, fab utilities, and data infrastructure can bottleneck output.

- Throughput and uptime are the biggest economic sensitivities in cost-of-ownership models.

- Service, spares, and field upgrades are part of the EUV platform strategy, not an afterthought.

- Faster cycle time accelerates learning. Learning speed is an economic variable, not just an engineering one.

- Shared pilot lines and consortia reduce duplicated early learning and speed up ramps when frontier development costs explode.

- Energy per wafer pass is now tracked as a performance metric, because utilities and cleanroom capacity can become limiting constraints.

GLOSSARY

- Coordinated manufacturability: Managing design and manufacturing as one economic system so bottlenecks don’t strand capital.

- Cost of ownership (CoO): A framework that totals capital and operating costs per unit of useful output, sensitive to throughput and uptime.

- Cost of technology: Industry shorthand for the total cost to produce a given generation of chips at target performance and yield.

- Installed base management: Service, spares, upgrades, and support revenue tied to the installed fleet of lithography tools.

- Field upgrade: A post-installation hardware/software upgrade that increases productivity or capability of an existing tool.

- Mask set: The full collection of photomasks required to pattern a chip’s layers; a significant NRE (non-recurring engineering) cost.

- Pilot line: A shared or dedicated facility for prototyping and de-risking process steps before mass production.

- Uptime / availability: The fraction of time a tool is ready for productive operation; a key driver of effective capacity.

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High-NA EUV moved closer to factory reality this week, but the bigger story is that AI demand is now reshaping the whole manufacturing stack around it. ASML supplied new readiness numbers, NVIDIA showed how AI is moving into lithography and verification flows, and Micron, SK hynix and Applied Materials made fresh moves around HBM, wafers and capacity. This episode explains why the competition is shifting from isolated tool milestones to coordinated manufacturability.

Key takeaways

- ASML said its High-NA EUV tools have processed about 500,000 wafers, are running at roughly 80% uptime, and target 90% uptime by the end of 2026.

- NVIDIA said Samsung, SK hynix and TSMC are using GPU-accelerated software for semiconductor design and manufacturing; Samsung and SK hynix were specifically named in computational lithography and physical verification.

- Micron said its 36GB 12H HBM4 is in high-volume production for NVIDIA Vera Rubin, with more than 2.8 TB/s bandwidth and about 20% better power efficiency.

- Micron completed the acquisition of PSMC’s Tongluo P5 site in Taiwan and plans to retrofit the existing cleanroom now, with a second similar-sized cleanroom planned by the end of fiscal 2026.

- Applied Materials said Micron and SK hynix will be founding partners at its EPIC Center, a planned $5 billion semiconductor equipment R&D effort.

- SK Group Chairman Chey Tae-won said AI-driven wafer shortages could continue until 2030 and remain above 20% because HBM consumes large amounts of wafer capacity.

- TSMC reported January-February 2026 revenue of NT$718.91 billion, up 29.9% year over year.

- Public reporting still lacks customer-by-customer High-NA insertion dates, layer choices and product-specific deployment schedules.

Glossary

Extreme Ultraviolet (EUV) lithography — Advanced chip-patterning technology using 13.5 nm light for leading-edge semiconductor manufacturing.

High Numerical Aperture (High-NA) EUV — The next EUV platform generation aimed at reducing process complexity and improving patterning economics at future nodes.

High Bandwidth Memory (HBM) — Stacked DRAM used near AI accelerators to deliver very high memory bandwidth.

HBM4 — The next major HBM generation, positioned for AI platforms such as NVIDIA Vera Rubin.

Dynamic Random Access Memory (DRAM) — Mainstream volatile memory used in servers, PCs, mobile devices and the base dies behind HBM.

Computational lithography — Software-intensive correction and optimization used to make mask patterns print accurately on wafers.

Physical verification — Design checks that confirm a chip layout can be manufactured reliably under process rules.

Advanced packaging — Technologies that connect or stack multiple chips closely to improve bandwidth, power and system performance.

Uptime — The share of time a tool is available and operating as intended in a manufacturing environment.

Cleanroom — A tightly controlled fabrication space designed to minimize particles, contamination and process variation.

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This week’s episode is a lighter but more revealing EUV week. The headlines are less about splashy new product launches and more about whether High-NA EUV, sub-2 nm patterning, and 2 nm capacity plans are becoming operationally credible. The through-line is simple: the bottleneck is moving from physics toward execution, cost, and integration.

Key takeaways:

- ASML says its High-NA EUV tools are ready for serious high-volume production insertion after processing about 500,000 wafers, with roughly 80% uptime today and a 90% year-end target.

- Intel is rethinking whether 18A should be offered more broadly to outside foundry customers, which could change future EUV tool loading and customer qualification plans.

- Rapidus raised ¥267.6 billion, including ¥100 billion from Japan’s IPA and ¥167.6 billion from 32 private-sector companies, to support 2 nm mass production plans for 2027.

- Chinese semiconductor executives are openly calling for a national lithography push during 2026–2030, underscoring that lithography remains a system-level bottleneck.

- IBM’s SPIE 2026 roadmap argues that below-2 nm progress depends on edge placement error, stochastic control, resist and mask behavior, and integration economics, not just raw resolution.

- The economic case for High-NA improves only if it removes multiple low-NA steps without losing uptime, yield, or integration margin.

- Advanced packaging, reticle stitching, and back-end alignment are becoming more central to EUV value as AI chip architectures get more complex.

- In a light-news week, the clearest competitive signal is who reduced uncertainty with official numbers and manufacturable process data.

Glossary:

Extreme Ultraviolet (EUV) lithography — A chip-patterning method that uses 13.5 nm light to print the smallest and most critical features.

High Numerical Aperture (High-NA) EUV — The next EUV platform generation, using 0.55 numerical aperture optics for higher resolution and fewer patterning steps at advanced nodes.

Edge placement error (EPE) — The difference between the intended feature edge location and the printed result on the wafer.

Stochastic defects — Random patterning failures caused by the probabilistic nature of photons, resist chemistry, and small feature dimensions.

k1 factor — A lithography scaling parameter used to describe how aggressively an optical system is being pushed toward its resolution limit.

Metal-oxide resist (MOR) — A photoresist class used in advanced EUV patterning, valued for resolution, roughness, and thin-film performance.

18A — Intel’s advanced process node, relevant here because broader foundry use would affect future EUV demand and capacity planning.

Reticle stitching — A method of joining adjacent exposure fields or patterned regions, often relevant for large-field packaging and advanced integration schemes.

This article was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

EUV scanners get the spotlight, but the wafer is the precision “canvas” that makes EUV possible. In this episode we trace how a silicon wafer is made—from ultra-pure polysilicon, to a single-crystal ingot, to slicing, polishing, and atomic-level cleaning—and then connect those steps to EUV’s brutal focus and defectivity budgets.

Key takeaways

- Wafers start from ultra-pure polysilicon, then become single-crystal ingots typically grown by the Czochralski method.

- The ingot is sliced into wafers, commonly using multi-wire sawing, followed by edge rounding, flattening, etching, and CMP polishing.

- “Flatness” has multiple scales: global thickness variation (micrometers), warp (tens of micrometers), site flatness (tens of nanometers), and nanotopography (single-digit nanometers).

- EUV’s limited depth of focus turns nanometer-scale height variation into printed CD and yield problems.

- Cleanliness is not just “low particles”; it includes trace metal contamination limits expressed in atoms per square centimeter.

- Wafer manufacturing is capital intensive and geographically concentrated among a small set of suppliers with sites across Asia, Europe, and the USA.

Glossary

- Wafer: A thin slice of single-crystal semiconductor that serves as the substrate for making integrated circuits.

- Czochralski method (CZ): Crystal growth method that pulls and rotates a seed crystal from molten silicon to form a cylindrical single-crystal ingot.

- MCz (Magnetic Czochralski): CZ growth with an applied magnetic field to control melt flow and improve uniformity.

- CMP (Chemical Mechanical Polishing): Combined chemical and abrasive polishing that produces a highly planar, mirror-finish wafer surface.

- GBIR / TTV: Global thickness variation metric describing overall wafer thickness non-uniformity.

- Warp / Bow: Measures of wafer out-of-plane deformation; important for handling and chucking.

- SFQR: A site flatness metric used to quantify flatness over defined local areas relevant to lithography fields.

- Nanotopography: Low-amplitude surface height variations over millimeter-scale windows that can drive focus fingerprints.

- TXRF / ICP-MS / SIMS: Analytical methods used to measure trace elemental contamination on wafer surfaces.

- FOUP: Front Opening Unified Pod; standardized wafer carrier used in fabs.

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This week’s episode is about EUV productivity: ASML’s kilowatt-class source milestone, and the process-side levers that can help turn more photons into more wafers. We also look at why AI-driven demand keeps EUV on the critical path, and how ASML is positioning “beyond EUV” for chiplet-era integration.

Key takeaways

- ASML says it has demonstrated a 1,000-watt EUV source under customer-representative requirements, up from roughly 600 watts today.

- ASML links higher source power to a productivity path from ~220 wafers per hour today to ~330 wafers per hour by 2030.

- ASML technologists described a roadmap path beyond 1,000 watts, citing ~1,500 watts as “clear” and “no fundamental reason” not to reach 2,000 watts.

- imec reports a 15–20% faster photo-speed for metal-oxide resists when oxygen during post-exposure bake rises from 21% to 50%, enabling dose reduction.

- Dose reduction and source-power scaling are complementary levers: fabs can spend gains on higher throughput or on yield/process margin.

- ASML’s 2025 annual report reports €32.7bn net sales, 52.8% gross margin, €4.7bn R&D spend, and 48 EUV systems sold (out of 535 total systems).

- ASML told Reuters it is expanding its portfolio “beyond EUV,” including interest in advanced packaging, 3D integration tooling, and potentially larger chip printing.

- Meta’s multi-year agreement with AMD, framed at up to 6GW of AMD Instinct GPUs, illustrates how hyperscaler AI buildouts can keep pressure on leading-edge and memory capacity.

Glossary

Extreme Ultraviolet (EUV) — 13.5 nm lithography used for the most advanced chip patterning.

Wafers per hour (WPH) — a scanner throughput metric describing processed wafers per hour.

Laser-produced plasma (LPP) — EUV light generation method using a laser to create plasma from tin droplets.

Carbon dioxide (CO₂) laser — high-power laser used in EUV source systems to drive the plasma.

Post-exposure bake (PEB) — thermal step after exposure that influences resist chemistry and final dimensions.

Metal-oxide resist (MOR) — EUV photoresist class often used for high-resolution, low-roughness patterning.

Pellicle — thin membrane protecting the photomask from contamination during exposure.

Advanced packaging — technologies that connect multiple dies (chiplets) via high-density bonding/interconnect.

Exposure dose — energy delivered to the resist; lower dose can improve throughput if other limits allow.

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This week’s episode tracks a split-cycle semiconductor economy: AI infrastructure keeps pulling leading-edge capacity forward, while consumer hardware feels unusually quiet. We look at what that means for Extreme Ultraviolet lithography decisions, from export-control pressure to new fab ramp plans. The common thread is allocation—of tools, service capacity, and calendar certainty.

Key takeaways:

- U.S. lawmakers are pushing for tighter, countrywide export controls on chipmaking tools to China, including attention to servicing and subcomponents.

- For EUV-heavy fabs, restrictions on spares and service can translate directly into effective capacity, not just future shipment limits.

- Rapidus’ business plan targets 2nm-class production in fiscal 2027 H2 and a ramp toward ~25,000 wafer starts per month within the first year.

- Rapidus says it must install and calibrate 200+ tools before yield stabilization—an execution test as much as a technology test.

- TrendForce cites a 2027–2028 window for High-NA EUV mass-production use, framing near-term planning without changing 2026 constraints.

- Tom’s Hardware argues AI infrastructure spending is reshaping consumer electronics, with pricing pressure and fewer “headline” launches.

- The episode’s focus: EUV is the allocation mechanism for the leading edge, and the “average product mix” assumption is breaking.

- Outlook watch: export-control rules on servicing, Rapidus milestone cadence, and whether consumer component pricing finds a new equilibrium.

Glossary:

- Extreme Ultraviolet (EUV) lithography — 13.5 nm lithography used for advanced semiconductor patterning.

- High Numerical Aperture (High-NA) EUV — Next-generation EUV tools with higher NA for improved resolution.

- Wafer starts per month — A fab capacity metric describing how many wafers begin processing each month.

- Wafer fab equipment (WFE) — The toolset used to manufacture semiconductor wafers (lithography, etch, deposition, metrology, etc.).

- Semiconductor manufacturing equipment (SME) — A broader term often used in policy contexts for chipmaking tools and key subcomponents.

- High-bandwidth memory (HBM) — Stacked DRAM designed for very high throughput, commonly paired with AI accelerators.

- Double data rate fifth generation (DDR5) — Mainstream DRAM interface standard used in PCs and servers.

- Yield stabilization — The phase where a new process reaches repeatable, economical defect and performance levels.

This article was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

Logic chips think, graphics chips see, memory chips remember—but under the hood, they’re all transistors optimized for different constraints.

In this episode we compare CPUs/SoCs, GPUs, and modern memory (SRAM, DRAM, NAND) through the lens of the EUV era: what the finished chips look like, what they’re used for, and why scaling shifts bottlenecks toward data movement and packaging.

Key takeaways

- “Logic” chips are dominated by wiring, power, and variability management—not just transistor switching speed.

- CPUs optimize for latency and control; GPUs optimize for throughput and sustained data-parallel work.

- SRAM is fast and refresh-free but expensive per bit, so it lives on logic dies as caches and registers.

- DRAM is far denser but needs refresh, so it becomes main memory and the stacked memory used in HBM.

- NAND flash is non-volatile storage that trades write/erase complexity and wear for ultra-low cost per bit.

- EUV shows up in finished logic chips as higher density, enabling more compute, more cache, and more specialized accelerators.

- EUV shows up in advanced DRAM as continued scaling, more bits per wafer, and improved power efficiency.

- As compute gets denser, performance increasingly depends on moving data efficiently—making memory technology and packaging central.

- HBM uses a wide, short-reach interface near the logic die to deliver extreme bandwidth with better energy per bit than long, high-speed board links.

Glossary

- Logic chip: A chip whose primary job is computation and control (CPUs, SoCs, accelerators).

- GPU (graphics processing unit): A throughput-oriented logic chip built from many parallel compute blocks.

- SRAM (static random access memory): Fast volatile memory built from bistable circuits; used mainly for on-chip cache.

- DRAM (dynamic random access memory): Dense volatile memory that stores bits as charge and requires refresh.

- NAND flash: Non-volatile memory used for storage; retains data without power by trapping charge.

- GDDR: Graphics DRAM family commonly used as external memory on GPU add-in boards.

- HBM (high bandwidth memory): 3D-stacked DRAM placed close to a logic die to provide very high bandwidth.

- Chiplet: A design style that splits a system into multiple dies connected by high-speed package links.

- Advanced packaging: Packaging technologies that integrate multiple dies closely (e.g., interposers and dense die-to-die links).

*This podcast was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.*

This week, Europe turns High-NA EUV from a roadmap slide into shared infrastructure as imec inaugurates NanoIC in Leuven. At the same time, Samsung switches from sampling to shipping HBM4, and capital plans from TSMC and Micron underline how tightly advanced nodes, packaging, and memory are now coupled. We close with a procurement reality check: when scarcity spreads beyond scanners, trust becomes an engineering variable.

Key takeaways:

- NanoIC launched at imec as Europe’s largest Chips Act pilot line, with a 2.5B euro investment package and major EU and national funding.

- imec expects its first High-NA lithography tool to arrive in mid-March 2026, with reporting pointing to March 18.

- NanoIC is positioned as an “EUV-ready” design-to-process loop, emphasizing PDKs, mask/data preparation, inspection, and defect learning speed.

- Samsung says it has started shipping HBM4 to customers, claiming 11.7 Gbps consistent speed and a path to 13 Gbps.

- HBM4 ramps translate into EUV load: more critical exposures, masks, resists, and metrology cycles needed to keep DRAM yields stable.

- TSMC approved about $44.962B in capital appropriations spanning advanced technology, advanced packaging, and fab construction systems.

- Micron’s New York megafab project progressed through January milestones, framed as a multi-decade, multi-fab domestic memory capacity hedge.

- Claus Aasholm argues “trust, but verify” and supplier transparency matter most when leverage shifts during tight cycles.

- Unclear: Samsung did not name HBM4 customers, and shipment volumes and yield trajectories were not disclosed.

Glossary:

EUV — Extreme Ultraviolet lithography using 13.5 nm light for advanced patterning.

High-NA — High numerical aperture EUV optics (NA ~0.55) enabling higher resolution but new field/mask trade-offs.

Numerical aperture (NA) — Optical parameter describing how much light an imaging system can accept; higher NA improves resolution.

HBM4 — Sixth-generation high-bandwidth memory stack used near AI accelerators for very high throughput.

PDK — Process Design Kit; a foundry/R&D-provided bundle of rules, models, and libraries for chip design.

OPC — Optical Proximity Correction; computational steps that pre-distort mask patterns to print correctly on wafer.

Pellicle — Thin membrane protecting EUV masks from particles, trading transmission for defect reduction.

Defectivity — Rate and types of defects introduced during processing that impact yield and reliability.

Digital twin — High-fidelity simulation model of a fab or tool used for optimization and predictive maintenance.

This podcast was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

ASML’s latest results show EUV bookings still dominate the conversation, while High-NA starts to surface in routine reporting. ZEISS is pushing actinic mask qualification throughput with AIMS EUV 3.0, and TSMC’s Japan plan signals that leading-edge EUV operations may spread further. This week’s theme is simple: the fastest feedback loop wins.

Key takeaways:

- ASML reported Q4 2025 net bookings of €13.2B, including €7.4B in EUV, and said it recognized revenue for two High-NA systems.

- ASML guided 2026 total net sales to €34–39B, signaling sustained tool demand.

- ASML said it will streamline Technology and IT; Reuters reported the plan could involve about 1,700 job cuts.

- ZEISS said AIMS EUV 3.0 is being deployed globally and delivers triple mask throughput versus the prior generation.

- ZEISS highlighted Digital FlexIllu to emulate scanner illumination for both low-NA EUV and High-NA workflows on one system.

- Reuters reported TSMC plans to mass-produce 3nm chips in Kumamoto, Japan; local media cited ~$17B investment while TSMC did not confirm the figure.

- Be cautious with AI-generated investor commentary around Japan’s chip push; verify claims against primary statements and major wires.

- Imec’s NanoIC pilot line released A14 logic and eDRAM pathfinding PDKs to support earlier design-technology co-optimization beyond 2nm.

- MarketsandMarkets (via PR Newswire) forecast EUV lithography growing from $15.84B (2026) to $30.36B by 2032.

- Unclear/publicly limited: customer-by-customer High-NA ramp schedules and mask defect printability budgets remain mostly non-disclosed.

Glossary:

EUV lithography — Extreme Ultraviolet lithography using ~13.5 nm light to pattern advanced semiconductor features.

High-NA — High numerical aperture EUV (0.55 NA class) enabling higher resolution than 0.33 NA EUV systems.

Numerical aperture — Optical parameter that sets resolution and depth of focus; higher NA increases resolution but tightens process margins.

Actinic mask qualification — Mask inspection/verification at the exposure wavelength regime to assess defect printability under scanner-like conditions.

AIMS — Aerial Image Measurement System; actinic tool used to evaluate EUV mask defect printability and scanner matching.

Scanner matching — Aligning mask qualification conditions with scanner optics and illumination to predict wafer printing behavior.

Illumination — The spatial/angular distribution of light used in exposure; affects imaging, process window, and defect printability.

Overlay — Alignment accuracy between patterned layers; becomes more difficult as pitches shrink and depth of focus narrows.

PDK — Process Design Kit; a set of design rules, device models, and flows enabling chip design for a given process technology.

Design-technology co-optimization — Joint optimization of design rules, layouts, and process integration to reduce risk and improve manufacturability.