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[015] Deep Dive Topic - Chip Nodes
"3 nanometer." "2 nanometer." "18A." These labels sound like simple size numbers, but they are really product-family names that bundle transistor architecture, power delivery, design rules, and manufacturing maturity. This episode explains what a node actually means in the EUV era, why Intel/TSMC/Samsung nodes do not line up, and how economics pushes modern chips toward variants, chiplets, and advanced packaging.
Key Takeaways
- A node name is a brand, not a ruler; the nanometer label is not a single physical dimension.
- Comparing nodes across companies by name alone is misleading; compare deliverables like transistor type, power delivery, and ramp maturity.
- TSMC positions N2 as its first nanosheet (gate-all-around) node with volume production starting in late 2025, and A16 adds a backside-power concept (SPR).
- Samsung's SF3 is a GAA-plus-EUV node, and Samsung has published a staged SF2 ramp plan (mobile first, then HPC and automotive).
- Intel 4 is Intel's first production node using EUV, and Intel 18A pairs RibbonFET (GAA) with PowerVia (backside power) with a stated HVM target in 2H 2025.
- DRAM "nodes" (1z, 1-alpha, 1-beta, 1-gamma, 1anm) are ten-nanometer-class generations, not comparable to logic nanometer labels; EUV is added selectively and increasingly.
- NAND scaling is primarily about vertical layer count; more layers raise etch and yield complexity but improve bits per wafer.
- EUV and High-NA EUV economics matter: tool cost, fab energy demand, and yield risk shape which products move first and why chiplets and packaging keep growing.
Glossary
- Node: A manufacturing generation name for a platform (rules, devices, interconnect, libraries, maturity), not a literal feature size.
- PPA: Power, performance, area - shorthand foundries use to summarize expected node improvements.
- FinFET: A transistor with a fin-shaped channel and a gate that wraps around multiple sides.
- Gate-all-around (GAA): A transistor where the gate surrounds the channel more completely (often implemented as nanosheets/nanoribbons).
- Nanosheet / nanoribbon: A GAA device shape using stacked thin channels to improve electrostatic control.
- Backside power delivery: Routing power from the back of the wafer to reduce front-side routing congestion and improve power integrity.
- EUV: Extreme ultraviolet lithography; used to pattern very small features, but it is capital- and energy-intensive.
- HVM: High-volume manufacturing; the phase when a node is producing at scale with stable yields.
- DRAM: Dynamic random-access memory; scaling is constrained by the repeating cell and capacitor/access-device integration.
- NAND: Non-volatile flash memory; scaling is largely vertical (more layers) and limited by deep etch, deposition, and yield.
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By EUV The Focal Point - Team"3 nanometer." "2 nanometer." "18A." These labels sound like simple size numbers, but they are really product-family names that bundle transistor architecture, power delivery, design rules, and manufacturing maturity. This episode explains what a node actually means in the EUV era, why Intel/TSMC/Samsung nodes do not line up, and how economics pushes modern chips toward variants, chiplets, and advanced packaging.
Key Takeaways
- A node name is a brand, not a ruler; the nanometer label is not a single physical dimension.
- Comparing nodes across companies by name alone is misleading; compare deliverables like transistor type, power delivery, and ramp maturity.
- TSMC positions N2 as its first nanosheet (gate-all-around) node with volume production starting in late 2025, and A16 adds a backside-power concept (SPR).
- Samsung's SF3 is a GAA-plus-EUV node, and Samsung has published a staged SF2 ramp plan (mobile first, then HPC and automotive).
- Intel 4 is Intel's first production node using EUV, and Intel 18A pairs RibbonFET (GAA) with PowerVia (backside power) with a stated HVM target in 2H 2025.
- DRAM "nodes" (1z, 1-alpha, 1-beta, 1-gamma, 1anm) are ten-nanometer-class generations, not comparable to logic nanometer labels; EUV is added selectively and increasingly.
- NAND scaling is primarily about vertical layer count; more layers raise etch and yield complexity but improve bits per wafer.
- EUV and High-NA EUV economics matter: tool cost, fab energy demand, and yield risk shape which products move first and why chiplets and packaging keep growing.
Glossary
- Node: A manufacturing generation name for a platform (rules, devices, interconnect, libraries, maturity), not a literal feature size.
- PPA: Power, performance, area - shorthand foundries use to summarize expected node improvements.
- FinFET: A transistor with a fin-shaped channel and a gate that wraps around multiple sides.
- Gate-all-around (GAA): A transistor where the gate surrounds the channel more completely (often implemented as nanosheets/nanoribbons).
- Nanosheet / nanoribbon: A GAA device shape using stacked thin channels to improve electrostatic control.
- Backside power delivery: Routing power from the back of the wafer to reduce front-side routing congestion and improve power integrity.
- EUV: Extreme ultraviolet lithography; used to pattern very small features, but it is capital- and energy-intensive.
- HVM: High-volume manufacturing; the phase when a node is producing at scale with stable yields.
- DRAM: Dynamic random-access memory; scaling is constrained by the repeating cell and capacitor/access-device integration.
- NAND: Non-volatile flash memory; scaling is largely vertical (more layers) and limited by deep etch, deposition, and yield.