This week’s EUV story is told through purchases: TSMC’s stepped-up 2026 capex, Micron’s decision to buy an existing cleanroom in Taiwan, and a U.S. megafab that won’t ship wafers until 2030. We connect those signals to the real bottleneck behind two-nanometer ramps: stable EUV hours, masks, and metrology. And we look at why High-NA matters less as a resolution headline and more as a cycle-time lever.

Key takeaways:

- TSMC guided 2026 capex to US$52–56B, with 70–80% allocated to advanced process technology and 10–20% to advanced packaging, test, and mask making.

- TSMC said its N2 (2nm) process entered high-volume manufacturing in 4Q 2025 at Hsinchu and Kaohsiung with good yield, with a faster ramp expected in 2026.

- TSMC said N2P volume production is scheduled for 2H 2026 and A16 volume production is on track for 2H 2026.

- TSMC said AI accelerators were a high-teens percentage of total revenue in 2025 and expects 2026 revenue growth close to 30% (USD terms).

- Micron signed an LOI to acquire PSMC’s P5 site in Tongluo for US$1.8B, including 300,000 square feet of 300mm cleanroom space, with meaningful DRAM output targeted for 2H 2027.

- Micron expects the Tongluo transaction to close by calendar Q2 2026, subject to agreements and regulatory approvals, and plans a phased DRAM equip-and-ramp.

- Micron held a groundbreaking for its New York megafab project, describing a US$100B complex with production expected to start in 2030 and a goal of producing 40% of its DRAM in the U.S.

- Culpium reported Apple is competing harder for leading-edge TSMC capacity as AI accelerator demand rises, with Nvidia potentially leading wafer purchases in some quarters.

- Reuters noted ASML briefly topped a US$500B market capitalization amid the semiconductor rally following TSMC’s capex outlook.

- No new official ASML EUV shipment or High-NA field update this week; the next major disclosure point is ASML’s January 28, 2026 results.

Glossary:

EUV — Extreme Ultraviolet lithography using 13.5 nm light for advanced patterning.

High-NA — High numerical aperture EUV optics (0.55 NA) enabling finer imaging and fewer multi-patterning steps on critical layers.

N2 — TSMC’s 2nm-class gate-all-around nanosheet process node.

N2P — Performance-enhanced variant of N2 scheduled for 2H 2026.

A16 — TSMC node featuring Super Power Rail (backside power delivery) targeting 2H 2026 volume production.

Scanner hours — A practical capacity metric: usable time on lithography tools after uptime and yield constraints.

Cleanroom — Ultra-controlled fab space whose construction, utilities, and staffing often limit expansion pace.

Mask making — Fabrication of reticles used in lithography; a common bottleneck for EUV ramps.

HBM — High Bandwidth Memory; stacked DRAM used with AI accelerators, driving demand for advanced DRAM capacity.

Advanced packaging — 2.5D/3D integration techniques that link logic and memory and consume significant capex and engineering effort.

This podcast was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.