Sign up to save your podcasts
Or
Share [022] Industry briefing - EUV The Focal Point
Share to email
Share to Facebook
Share to X
Share to email
Share to Facebook
Share to X
Or
[022] Industry briefing - EUV The Focal Point
This podcast was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.
ASML’s latest results show EUV bookings still dominate the conversation, while High-NA starts to surface in routine reporting. ZEISS is pushing actinic mask qualification throughput with AIMS EUV 3.0, and TSMC’s Japan plan signals that leading-edge EUV operations may spread further. This week’s theme is simple: the fastest feedback loop wins.
Key takeaways:
- ASML reported Q4 2025 net bookings of €13.2B, including €7.4B in EUV, and said it recognized revenue for two High-NA systems.
- ASML guided 2026 total net sales to €34–39B, signaling sustained tool demand.
- ASML said it will streamline Technology and IT; Reuters reported the plan could involve about 1,700 job cuts.
- ZEISS said AIMS EUV 3.0 is being deployed globally and delivers triple mask throughput versus the prior generation.
- ZEISS highlighted Digital FlexIllu to emulate scanner illumination for both low-NA EUV and High-NA workflows on one system.
- Reuters reported TSMC plans to mass-produce 3nm chips in Kumamoto, Japan; local media cited ~$17B investment while TSMC did not confirm the figure.
- Be cautious with AI-generated investor commentary around Japan’s chip push; verify claims against primary statements and major wires.
- Imec’s NanoIC pilot line released A14 logic and eDRAM pathfinding PDKs to support earlier design-technology co-optimization beyond 2nm.
- MarketsandMarkets (via PR Newswire) forecast EUV lithography growing from $15.84B (2026) to $30.36B by 2032.
- Unclear/publicly limited: customer-by-customer High-NA ramp schedules and mask defect printability budgets remain mostly non-disclosed.
Glossary:
EUV lithography — Extreme Ultraviolet lithography using ~13.5 nm light to pattern advanced semiconductor features.
High-NA — High numerical aperture EUV (0.55 NA class) enabling higher resolution than 0.33 NA EUV systems.
Numerical aperture — Optical parameter that sets resolution and depth of focus; higher NA increases resolution but tightens process margins.
Actinic mask qualification — Mask inspection/verification at the exposure wavelength regime to assess defect printability under scanner-like conditions.
AIMS — Aerial Image Measurement System; actinic tool used to evaluate EUV mask defect printability and scanner matching.
Scanner matching — Aligning mask qualification conditions with scanner optics and illumination to predict wafer printing behavior.
Illumination — The spatial/angular distribution of light used in exposure; affects imaging, process window, and defect printability.
Overlay — Alignment accuracy between patterned layers; becomes more difficult as pitches shrink and depth of focus narrows.
PDK — Process Design Kit; a set of design rules, device models, and flows enabling chip design for a given process technology.
Design-technology co-optimization — Joint optimization of design rules, layouts, and process integration to reduce risk and improve manufacturability.
View all episodes
By EUV The Focal Point - TeamThis podcast was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.
ASML’s latest results show EUV bookings still dominate the conversation, while High-NA starts to surface in routine reporting. ZEISS is pushing actinic mask qualification throughput with AIMS EUV 3.0, and TSMC’s Japan plan signals that leading-edge EUV operations may spread further. This week’s theme is simple: the fastest feedback loop wins.
Key takeaways:
- ASML reported Q4 2025 net bookings of €13.2B, including €7.4B in EUV, and said it recognized revenue for two High-NA systems.
- ASML guided 2026 total net sales to €34–39B, signaling sustained tool demand.
- ASML said it will streamline Technology and IT; Reuters reported the plan could involve about 1,700 job cuts.
- ZEISS said AIMS EUV 3.0 is being deployed globally and delivers triple mask throughput versus the prior generation.
- ZEISS highlighted Digital FlexIllu to emulate scanner illumination for both low-NA EUV and High-NA workflows on one system.
- Reuters reported TSMC plans to mass-produce 3nm chips in Kumamoto, Japan; local media cited ~$17B investment while TSMC did not confirm the figure.
- Be cautious with AI-generated investor commentary around Japan’s chip push; verify claims against primary statements and major wires.
- Imec’s NanoIC pilot line released A14 logic and eDRAM pathfinding PDKs to support earlier design-technology co-optimization beyond 2nm.
- MarketsandMarkets (via PR Newswire) forecast EUV lithography growing from $15.84B (2026) to $30.36B by 2032.
- Unclear/publicly limited: customer-by-customer High-NA ramp schedules and mask defect printability budgets remain mostly non-disclosed.
Glossary:
EUV lithography — Extreme Ultraviolet lithography using ~13.5 nm light to pattern advanced semiconductor features.
High-NA — High numerical aperture EUV (0.55 NA class) enabling higher resolution than 0.33 NA EUV systems.
Numerical aperture — Optical parameter that sets resolution and depth of focus; higher NA increases resolution but tightens process margins.
Actinic mask qualification — Mask inspection/verification at the exposure wavelength regime to assess defect printability under scanner-like conditions.
AIMS — Aerial Image Measurement System; actinic tool used to evaluate EUV mask defect printability and scanner matching.
Scanner matching — Aligning mask qualification conditions with scanner optics and illumination to predict wafer printing behavior.
Illumination — The spatial/angular distribution of light used in exposure; affects imaging, process window, and defect printability.
Overlay — Alignment accuracy between patterned layers; becomes more difficult as pitches shrink and depth of focus narrows.
PDK — Process Design Kit; a set of design rules, device models, and flows enabling chip design for a given process technology.
Design-technology co-optimization — Joint optimization of design rules, layouts, and process integration to reduce risk and improve manufacturability.