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[023] Industry briefing - EUV The Focal Point
*This podcast was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.*
This week, Europe turns High-NA EUV from a roadmap slide into shared infrastructure as imec inaugurates NanoIC in Leuven. At the same time, Samsung switches from sampling to shipping HBM4, and capital plans from TSMC and Micron underline how tightly advanced nodes, packaging, and memory are now coupled. We close with a procurement reality check: when scarcity spreads beyond scanners, trust becomes an engineering variable.
Key takeaways:
- NanoIC launched at imec as Europe’s largest Chips Act pilot line, with a 2.5B euro investment package and major EU and national funding.
- imec expects its first High-NA lithography tool to arrive in mid-March 2026, with reporting pointing to March 18.
- NanoIC is positioned as an “EUV-ready” design-to-process loop, emphasizing PDKs, mask/data preparation, inspection, and defect learning speed.
- Samsung says it has started shipping HBM4 to customers, claiming 11.7 Gbps consistent speed and a path to 13 Gbps.
- HBM4 ramps translate into EUV load: more critical exposures, masks, resists, and metrology cycles needed to keep DRAM yields stable.
- TSMC approved about $44.962B in capital appropriations spanning advanced technology, advanced packaging, and fab construction systems.
- Micron’s New York megafab project progressed through January milestones, framed as a multi-decade, multi-fab domestic memory capacity hedge.
- Claus Aasholm argues “trust, but verify” and supplier transparency matter most when leverage shifts during tight cycles.
- Unclear: Samsung did not name HBM4 customers, and shipment volumes and yield trajectories were not disclosed.
Glossary:
EUV — Extreme Ultraviolet lithography using 13.5 nm light for advanced patterning.
High-NA — High numerical aperture EUV optics (NA ~0.55) enabling higher resolution but new field/mask trade-offs.
Numerical aperture (NA) — Optical parameter describing how much light an imaging system can accept; higher NA improves resolution.
HBM4 — Sixth-generation high-bandwidth memory stack used near AI accelerators for very high throughput.
PDK — Process Design Kit; a foundry/R&D-provided bundle of rules, models, and libraries for chip design.
OPC — Optical Proximity Correction; computational steps that pre-distort mask patterns to print correctly on wafer.
Pellicle — Thin membrane protecting EUV masks from particles, trading transmission for defect reduction.
Defectivity — Rate and types of defects introduced during processing that impact yield and reliability.
Digital twin — High-fidelity simulation model of a fab or tool used for optimization and predictive maintenance.
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By EUV The Focal Point - Team*This podcast was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.*
This week, Europe turns High-NA EUV from a roadmap slide into shared infrastructure as imec inaugurates NanoIC in Leuven. At the same time, Samsung switches from sampling to shipping HBM4, and capital plans from TSMC and Micron underline how tightly advanced nodes, packaging, and memory are now coupled. We close with a procurement reality check: when scarcity spreads beyond scanners, trust becomes an engineering variable.
Key takeaways:
- NanoIC launched at imec as Europe’s largest Chips Act pilot line, with a 2.5B euro investment package and major EU and national funding.
- imec expects its first High-NA lithography tool to arrive in mid-March 2026, with reporting pointing to March 18.
- NanoIC is positioned as an “EUV-ready” design-to-process loop, emphasizing PDKs, mask/data preparation, inspection, and defect learning speed.
- Samsung says it has started shipping HBM4 to customers, claiming 11.7 Gbps consistent speed and a path to 13 Gbps.
- HBM4 ramps translate into EUV load: more critical exposures, masks, resists, and metrology cycles needed to keep DRAM yields stable.
- TSMC approved about $44.962B in capital appropriations spanning advanced technology, advanced packaging, and fab construction systems.
- Micron’s New York megafab project progressed through January milestones, framed as a multi-decade, multi-fab domestic memory capacity hedge.
- Claus Aasholm argues “trust, but verify” and supplier transparency matter most when leverage shifts during tight cycles.
- Unclear: Samsung did not name HBM4 customers, and shipment volumes and yield trajectories were not disclosed.
Glossary:
EUV — Extreme Ultraviolet lithography using 13.5 nm light for advanced patterning.
High-NA — High numerical aperture EUV optics (NA ~0.55) enabling higher resolution but new field/mask trade-offs.
Numerical aperture (NA) — Optical parameter describing how much light an imaging system can accept; higher NA improves resolution.
HBM4 — Sixth-generation high-bandwidth memory stack used near AI accelerators for very high throughput.
PDK — Process Design Kit; a foundry/R&D-provided bundle of rules, models, and libraries for chip design.
OPC — Optical Proximity Correction; computational steps that pre-distort mask patterns to print correctly on wafer.
Pellicle — Thin membrane protecting EUV masks from particles, trading transmission for defect reduction.
Defectivity — Rate and types of defects introduced during processing that impact yield and reliability.
Digital twin — High-fidelity simulation model of a fab or tool used for optimization and predictive maintenance.