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This week’s episode looks at how artificial intelligence demand is feeding back into semiconductor manufacturing itself. Intel’s Terafab move, TSMC and Samsung’s new numbers, tighter equipment politics around China, and Japan’s fresh support for Rapidus all point to the same conclusion: EUV is now part of a wider manufacturing-system battle. The focus topic explains why fabs are using AI not only to sell chips, but to stabilize yield, shorten learning cycles, and make scarce lithography capacity more productive.

Key takeaways

- Intel formally joined Elon Musk’s Terafab effort with Tesla and SpaceX, turning a previously speculative foundry link into an announced partnership.

- The proposed U.S. MATCH Act would extend pressure from already-banned EUV exports to DUV equipment sales and servicing, making support capacity itself a policy lever.

- TSMC reported March 2026 revenue of NT$415.19 billion and first-quarter revenue of NT$1.134 trillion, up 35.1% year over year.

- Samsung guided first-quarter 2026 sales of about 133 trillion won and operating profit of about 57.2 trillion won.

- Samsung says it is feeding wafer-level pattern data back into design, using agentic AI for diagnostics, and running a Pyeongtaek fab digital twin on NVIDIA Omniverse.

- Gartner forecasts 2026 semiconductor revenue at $1.3202 trillion, with memory revenue at $633.3 billion and meaningful pricing relief not expected until late 2027.

- Japan approved another 631.5 billion yen for Rapidus, while Rapidus also announced NEDO approval for its FY2026 plan and opened new analysis and chiplet facilities.

- One relevant thread remains unclear: Samsung’s reported 1 nm forksheet roadmap is still unofficial and should be treated as directional rather than confirmed.

Glossary

EUV — Extreme Ultraviolet lithography used for the most advanced patterning layers in semiconductor manufacturing.

DUV — Deep Ultraviolet lithography, an older but still strategically important class of patterning tools.

High-NA — High Numerical Aperture EUV, the next EUV platform aimed at higher resolution and fewer multi-patterning steps on critical layers.

HBM — High Bandwidth Memory, a stacked memory architecture used heavily in AI accelerators.

HBM4E — An expected enhanced generation of HBM4 with tighter quality and yield requirements for advanced memory production.

Digital twin — A software-based virtual replica of a fab or process used for monitoring, simulation, and risk reduction.

MES — Manufacturing Execution System software that tracks and coordinates production on the fab floor.

PDK — Process Design Kit, the rule set and models chip designers need to design for a specific manufacturing process.

Chiplet — A smaller die designed to be combined with other dies in an advanced package rather than built as one large monolithic chip.

TAT — Turnaround Time, the elapsed time needed to move a design or wafer flow through a development or production cycle.