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[037] Industry briefing - EUV The Focal Point
This post was created using AI. Please check the information if you want to use it as a basis for decision-making.
This episode looks at the split opening in advanced lithography: TSMC is extending the life of today’s EUV platform while ASML ramps Low-NA output and Intel tries to turn 14A into a real external foundry win. The focus is not whether High-NA EUV matters; it is when its cost and integration risk are justified. SK hynix’s record quarter shows why memory capacity keeps pulling on the same EUV ecosystem.
Key takeaways
- TSMC announced A13 for 2029 as a direct shrink of A14, with 6% area savings and full A14 design-rule compatibility.
- TSMC introduced N2U for 2028, targeting 3-4% speed gains or 8-10% power reduction and 1.02-1.03X logic density over N2P.
- TSMC’s 2028 14-reticle CoWoS target would combine about 10 compute dies and 20 HBM stacks, shifting more scaling value to packaging.
- Tesla’s Terafab plan now names Intel 14A, making it Intel’s first major named external customer for that technology.
- Intel said 14A maturity, yield, and performance are outpacing 18A at a comparable stage, while early design commitments remain expected from H2 2026 into H1 2027.
- SK hynix reported KRW 52.5763T revenue, KRW 37.6103T operating profit, and a 72% operating margin in Q1 2026.
- ASML says it is driving at least 60 Low-NA EUV systems in 2026 and at least 80 systems of Low-NA capacity in 2027.
- No fresh material Rapidus update was found after the previously covered April 11 funding and facility announcements.
Glossary
Extreme Ultraviolet (EUV) — 13.5 nm lithography used for critical layers in advanced semiconductor manufacturing.
High Numerical Aperture (High-NA) EUV — Next-generation EUV with higher optical numerical aperture, improving resolution but adding cost and integration complexity.
Low-NA EUV — The current production EUV platform used broadly for advanced logic and DRAM manufacturing.
Chip on Wafer on Substrate (CoWoS) — TSMC advanced packaging technology that integrates large compute dies and memory stacks on an interposer/substrate.
High Bandwidth Memory (HBM) — Stacked DRAM placed near accelerators to provide very high data bandwidth.
Process Design Kit (PDK) — Foundry-provided design rules, device models, and verification data for a specific process.
Design-Technology Co-Optimization (DTCO) — Joint optimization of chip design choices and manufacturing process constraints.
Reticle — The photomask field used in lithography; reticle limits affect the maximum size of exposed dies or stitched packages.
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By EUV The Focal Point - TeamThis post was created using AI. Please check the information if you want to use it as a basis for decision-making.
This episode looks at the split opening in advanced lithography: TSMC is extending the life of today’s EUV platform while ASML ramps Low-NA output and Intel tries to turn 14A into a real external foundry win. The focus is not whether High-NA EUV matters; it is when its cost and integration risk are justified. SK hynix’s record quarter shows why memory capacity keeps pulling on the same EUV ecosystem.
Key takeaways
- TSMC announced A13 for 2029 as a direct shrink of A14, with 6% area savings and full A14 design-rule compatibility.
- TSMC introduced N2U for 2028, targeting 3-4% speed gains or 8-10% power reduction and 1.02-1.03X logic density over N2P.
- TSMC’s 2028 14-reticle CoWoS target would combine about 10 compute dies and 20 HBM stacks, shifting more scaling value to packaging.
- Tesla’s Terafab plan now names Intel 14A, making it Intel’s first major named external customer for that technology.
- Intel said 14A maturity, yield, and performance are outpacing 18A at a comparable stage, while early design commitments remain expected from H2 2026 into H1 2027.
- SK hynix reported KRW 52.5763T revenue, KRW 37.6103T operating profit, and a 72% operating margin in Q1 2026.
- ASML says it is driving at least 60 Low-NA EUV systems in 2026 and at least 80 systems of Low-NA capacity in 2027.
- No fresh material Rapidus update was found after the previously covered April 11 funding and facility announcements.
Glossary
Extreme Ultraviolet (EUV) — 13.5 nm lithography used for critical layers in advanced semiconductor manufacturing.
High Numerical Aperture (High-NA) EUV — Next-generation EUV with higher optical numerical aperture, improving resolution but adding cost and integration complexity.
Low-NA EUV — The current production EUV platform used broadly for advanced logic and DRAM manufacturing.
Chip on Wafer on Substrate (CoWoS) — TSMC advanced packaging technology that integrates large compute dies and memory stacks on an interposer/substrate.
High Bandwidth Memory (HBM) — Stacked DRAM placed near accelerators to provide very high data bandwidth.
Process Design Kit (PDK) — Foundry-provided design rules, device models, and verification data for a specific process.
Design-Technology Co-Optimization (DTCO) — Joint optimization of chip design choices and manufacturing process constraints.
Reticle — The photomask field used in lithography; reticle limits affect the maximum size of exposed dies or stitched packages.