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This week’s episode is a light scanner-shipment week, but a strong roadmap and economics week. The central theme is coexistence: DUV, Low-NA EUV, High-NA EUV, and advanced packaging are becoming complementary tools rather than sequential replacements. The episode looks at TSMC’s A16 timing, Samsung’s record chip results, Big Tech’s AI spending pressure, and why ASML’s workhorse Low-NA fleet still matters.

Key takeaways:

- TSMC’s A16 is described as ready for production in 2026, but volume production is now aligned to 2027 because customer ramp timing drives the schedule.

- TSMC’s A12 and A13 roadmap through 2029 continues to avoid High-NA EUV, reinforcing a strategy of extending current Low-NA EUV capability.

- TrendForce frames TSMC’s High-NA deferral as a Low-NA strength story rather than a near-term collapse in EUV demand.

- ASML’s near-term EUV economics remain tied to Low-NA output and upgrades, including at least 60 Low-NA EUV systems in 2026 and a path toward about 80 in 2027.

- Samsung reported KRW 133.9 trillion in Q1 revenue and KRW 57.2 trillion in operating profit, with its Device Solutions division contributing KRW 53.7 trillion of operating profit.

- Samsung said it started mass product sales of HBM4 and SOCAMM2 for NVIDIA’s Vera Rubin platform and plans first HBM4E samples in Q2 2026.

- Reuters Breakingviews reported that Alphabet, Amazon, Meta, and Microsoft may invest up to $725 billion this year, while Alphabet said cloud revenue was limited by processor constraints.

- TSMC’s SoIC roadmap points from 6-micron hybrid-bonding pitch in 2025 toward 4.5 microns in 2029, showing that packaging is increasingly part of the scaling answer.

- No major new official ASML scanner shipment announcement surfaced this week; the episode therefore emphasizes roadmap timing, customer adoption, and cost-per-good-die logic.

Glossary:

EUV — Extreme Ultraviolet lithography, the 13.5-nanometer exposure technology used for the most critical layers in advanced chips.

Low-NA EUV — Current-generation EUV lithography using a 0.33 numerical aperture optical system.

High-NA EUV — Next-generation EUV lithography using a 0.55 numerical aperture system for finer patterning on selected critical layers.

DUV — Deep Ultraviolet lithography, still used for many layers even in advanced chips.

A16 — TSMC’s data-center-oriented node family using Super Power Rail backside power delivery.

Backside power delivery — A power-routing approach that moves power rails to the back of the wafer to improve routing and power integrity.

HBM4 — Fourth-generation High Bandwidth Memory for AI accelerators and high-performance computing systems.

SoIC — TSMC’s System on Integrated Chips 3D stacking technology using hybrid bonding for vertical die-to-die connections.

CoWoS — TSMC’s Chip on Wafer on Substrate advanced packaging platform for large AI and HPC packages.

Cost per good die — The manufacturing cost of each functional die after yield, cycle time, tool cost, and process complexity are included.