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This week’s episode looks at EUV less as a single-tool story and more as a capacity, customer, and capital-allocation story. Apple’s reported Intel and Samsung outreach, Samsung’s 2nm foundry push, SK Hynix customer-financing talks, and TSMC’s low-NA roadmap strategy all point to the same conclusion: the bottleneck is now economic and geopolitical as much as technical.

Key takeaways:

- Previous scripts or sources were not available in the workspace, so non-repetition was handled on a best-effort basis.

- Reuters relayed a Wall Street Journal report that Apple and Intel reached a preliminary chip-making deal, but Intel and Apple declined comment and the product scope remains unclear.

- Reuters also relayed Bloomberg reporting that Apple explored U.S. chipmaking with Intel and Samsung, while Reuters could not independently verify the report.

- Samsung reported Q1 2026 consolidated revenue of KRW 133.9 trillion and operating profit of KRW 57.2 trillion.

- Samsung said its foundry business plans full utilization of advanced-node lines in Q2 2026, broader 2nm customer engagement, and second-generation 2nm mobile ramp in H2 2026.

- Reuters reported that Samsung expects more advanced 2nm logic customers and is reviewing a second Taylor, Texas fab while targeting first Taylor volume production in 2027.

- Reuters reported that SK Hynix customers have proposed funding production lines and ASML EUV tools, reflecting extreme tightness in AI-driven memory supply.

- TSMC introduced A13, A12, and N2U, with N2U planned for 2028 and A13/A12 planned for 2029, while continuing to extract gains from existing EUV platforms.

- ASML reported Q1 2026 net sales of €8.8 billion and updated 2026 net sales guidance to €36 billion–€40 billion.

- Apple A20 and C2 modem items remain rumors; they were used only as directional signals for custom-silicon and packaging demand.

Glossary:

Extreme Ultraviolet (EUV) — lithography using 13.5 nm light to pattern the most critical layers in advanced chips.

High Numerical Aperture (High-NA) EUV — ASML’s newer 0.55 NA EUV platform designed for finer resolution and future sub-2nm logic and advanced memory.

Low numerical aperture (low-NA) EUV — the 0.33 NA EUV platform widely used for current leading-edge logic and memory production.

Hyper-NA — a possible future EUV generation above High-NA, still more of a 2030s feasibility topic than a near-term production tool.

2nm — an advanced process-node class using nanosheet or gate-all-around transistor structures, with naming varying by foundry.

Wafer-Level Multi-Chip Module (WMCM) — a packaging approach that integrates components at wafer level before singulation.

High-Bandwidth Memory (HBM) — stacked DRAM used beside AI accelerators to provide very high data bandwidth.

CoWoS — TSMC’s Chip-on-Wafer-on-Substrate advanced packaging family for large AI and high-performance computing packages.

Backside power delivery — a routing approach that moves power delivery to the wafer backside to reduce congestion and improve performance.

Foundry — a manufacturer that produces chips designed by external customers.