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Here are the show notes for Episode 0 “Sic Parvis Magna” (“Greatness From Small Beginnings”).
We’re structuring each podcast episode (loosely) in three parts:
Our “Mainframe” topic is about an SPE to z/OS 2.1 for SDSF. APARs mentioned were:
Our “Performance” topic is about detecting address spaces in support of FPGA cards. Some useful information on the new PCIE and FPGHWAM address spaces is
You can reach Marna on Twitter as mwalle and by email. You can reach Martin on Twitter as martinpacker and by email. Or you can leave a comment below.
Here are the show notes for Episode 0 “Sic Parvis Magna” (“Greatness From Small Beginnings”).
We’re structuring each podcast episode (loosely) in three parts:
Our “Mainframe” topic is about an SPE to z/OS 2.1 for SDSF. APARs mentioned were:
Our “Performance” topic is about detecting address spaces in support of FPGA cards. Some useful information on the new PCIE and FPGHWAM address spaces is
You can reach Marna on Twitter as mwalle and by email. You can reach Martin on Twitter as martinpacker and by email. Or you can leave a comment below.