Intel Chip Chat

Intel Chip Chat

By Intel CorporationTechnology
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Intel Chip Chat episodes

  • HPE Enables Enterprise Blockchain with Intel Architecture - Intel® Chip Chat episode 563
    Raphael Davison, Worldwide Director of Blockchain for HPE, joins us live from HPE Discover in Madrid. Davison is responsible for leading HPE's worldwide team to deliver differentiated blockchain technology services. In this interview, Davison talks about what it means to be HPE's worldwide director of blockchain, why blockchain is of interest to HPE's enterprise customers (it's not just about bitcoin), and how products like HPE's Mission Critical Distributed Ledger Technology are enabling blockchain for more customers. For more information on HPE's Intel-based blockchain solutions, please visit hpe.com/security.
    13 min
  • Jump Start AI with Intel Xeon, Transfer Learning, and Open Source - Intel® Chip Chat episode 562
    Dr. Bob Rogers, Chief Data Scientist for Analytics and AI, leads the portion of Intel’s business that helps customers and end users achieve their data analytics goals in this new, data-driven world. To understand where customers are in their analytics journey, Intel uses the analytics maturity curve to help customers appropriately expand their capabilities and infrastructure for what they need to solve. Dr. Rogers shares that most enterprises do not have a lot of data at their fingertips, but most have an AI solution they need now. Dr. Rogers says the good news is many enterprises use Intel® Xeon® infrastructure, and with that, they can already run their analytics workloads. They can start with transfer learning, a leading methodology to jump start an analytics program. Intel has also invested in optimized software and AI frameworks available through open source, such as BigDL, Intel® Optimization of Caffe* and TensorFlow*, which all run on Intel Xeon.
    Links:
    * Visit intel.com/analytics and view the Intel® One Minute Misconceptions series which exposes common misconceptions around advanced analytics.
    * Learn how Intel and Fero Labs are empowering advanced analytics and machine learning in manufacturing in this solution brief: http://intel.ly/2BBXG9I
    10 min
  • Jump Start AI with Intel Xeon, Transfer Learning, and Open Source - Intel® Chip Chat episode 562
    Dr. Bob Rogers, Chief Data Scientist for Analytics and AI, leads the portion of Intel’s business that helps customers and end users achieve their data analytics goals in this new, data-driven world. To understand where customers are in their analytics journey, Intel uses the analytics maturity curve to help customers appropriately expand their capabilities and infrastructure for what they need to solve. Dr. Rogers shares that most enterprises do not have a lot of data at their fingertips, but most have an AI solution they need now. Dr. Rogers says the good news is many enterprises use Intel® Xeon® infrastructure, and with that, they can already run their analytics workloads. They can start with transfer learning, a leading methodology to jump start an analytics program. Intel has also invested in optimized software and AI frameworks available through open source, such as BigDL, Intel® Optimization of Caffe* and TensorFlow*, which all run on Intel Xeon.
    Links:
    * Visit intel.com/analytics and view the Intel® One Minute Misconceptions series which exposes common misconceptions around advanced analytics.
    * Learn how Intel and Fero Labs are empowering advanced analytics and machine learning in manufacturing in this solution brief: http://intel.ly/2BBXG9I
    10 min
  • IDT HEVC Compression Optimizes Streaming Media Bandwidth - Intel® Chip Chat episode 558
    David Ko, Senior Product Marketing Manager at GigPeak, joins Intel Chip Chat to discuss how GigPeak’s new HEVC compression solution addresses many of the challenges of streaming video. GigPeak has developed an HEVC compression algorithm specifically optimized to run on the Intel® Xeon® Processor E3 which uses significantly less power and offers a lower cost per stream. The explosion of video streaming puts huge pressure on network bandwidth. HEVC compression delivers bandwidth savings but requires more processing power, space, and cooling requirements. GigPeak’s HEVC algorithm, optimized for the low-power Intel Xeon Processor E3 family with Integrated Iris Pro graphics, addresses many of the problems operators and vendors face when trying to support HEVC.
    Note: At the time of this podcast's recording, IDT's acquisition of GigPeak was not yet complete.
    8 min
  • Intel® Xeon® Processors for Workstations Accelerate Innovation - Intel® Chip Chat episode 556
    Ricky Branner, Director of High Performance Scale and Emerging Business for Intel, joins us to discuss the new Intel® Xeon® Scalable and Intel Xeon W processors for workstations. An engineer at heart with more than 30 years in the technology industry, Branner helps to drive Intel's workstation business segment -- in his words, to "enable creators to really make a difference." In this interview, Branner outlines the capabilities of Intel's new workstation processors, talks about the heavyweight workloads for which customers are turning to workstations, and gives a preview of what's coming up next from Intel's workstation team. For more information on Intel Xeon Scalable and Intel Xeon W processors for workstations, please visit http://intel.com/xeonworkstations.
    Configurations: Intel Xeon Scalable processor: Up to 2.71X performance versus a 4 year old workstation. Config: Based on best-published two-socket SPECfp*_rate_base2006 result submitted to/published at http://www.spec.org/cpu2006/results/ as of 11 July 2017. New configuration: 1-Node, 2 x Intel® Xeon® Platinum 8180 Processor on Huawei 2288H V5 with 384 GB total memory on SUSE Linux Enterprise Server 12 SP2 (x86_64) Kernel 4.4.21-69-default, using C/C++ and Fortran: Version 17.0.0.098 of Intel C/C++ and Intel Fortran Compiler for Linux. Source: submitted to www.spec.org, SPECfp*_rate_base2006 Score: 1850 compared to 1-Node, 1 node, 2x Intel® Xeon® E5-2697 v2 on Cisco Systems Cisco UCS C220 M3 using 128 GB total memory on Red Hat Enterprise Linux Server release 6.4 (Santiago) 2.6.32-358.el6.x86_64 C/C++: Version 14.0.0.080 of Intel C++ Studio XE for Linux; Fortran: Version 4.0.0.080 of Intel Fortran Studio XE for Linux. Source: https://www.spec.org/cpu2006/results/res2013q4/cpu2006-20130923-26455.html SPECfp*_rate_base2006 Score: 682
    Intel Xeon W processor: Up to 1.87X performance versus a 4 year old workstation. Config: 1-Node, 1 x Intel® Xeon® Processor E5-1680 v2 on Romley-EP with 64 GB Total Memory on CentOS release 6.9 2.6.32-431.el6.x86_64 using C/C++: Version 14.0.0.080 of Intel C/C++ studio XE for Linux, AVX Data Source: Request Number: 3822, Benchmark: SPECint*_rate_base2006, Score: 332 Higher is better; vs 1-Node, 1 x Intel® Xeon® W-2155 Processor on Basin Falls RVP with 128 GB Total Memory on Red Hat Enterprise Linux* 7.3 using CPU2006-1.2-ic17.0u3-lin-binaries-20170411. Data Source: Request Number: 3821, Benchmark: SPECint*_rate_base2006, Score: 622 Higher is better
    Results have been estimated based on internal Intel analysis and are provided for informational purposes only. Any difference in system hardware or software design or configuration may affect actual performance. Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. For more information go to http://www.intel.com/performance/datacenter.
    9 min
  • Intel® Nervana™ AI Academy Broadens Access to AI Training - Intel® Chip Chat episode 554
    Daman Oberoi, Program Manager for the Intel® Nervana™ AI Academy, joins us to discuss educating today's and tomorrow's developers and data scientists. The Intel Nervana AI Academy is a one-stop shop for people interested in AI and provides training for developers, students, professors, and scientists at a variety of skill levels. In this interview, Oberoi updates on the AI Academy's progress since its November 2016 start, including the launch of the AI Academy for Professors. Oberoi further speaks to the diverse audiences reached by the AI Academy throughout the world. Oberoi additionally notes the AI Academy's strong training and community offerings for the developer audience, which include worldwide meetups, training webinars, framework optimizations, Kaggle competitions, ML/DL learning kits, and access to the Intel® Nervana™ Devcloud. For more information on the Intel Nervana AI Academy, please visit http://software.intel.com/AI.
    10 min
  • Intel® Omni-Path Architecture: Speed and Scale for HPC Workloads - Intel® Chip Chat episode 553
    Scott Misage, General Manager for the Intel® Omni-Path Business Unit, joins us for an update on Intel® Omni-Path Architecture (Intel® OPA). Intel OPA, part of Intel® Scalable System Framework, is a high-performance fabric enabling the responsiveness, throughput, and scalability required by today's and tomorrow's most-demanding high performance computing (HPC) workloads. In this interview, Misage talks about market uptake in Intel OPA's first year of availability, reports on some of the first HPC deployments using the Intel Xeon Scalable platform and Intel OPA, and gives a sneak peek of what Intel OPA will be talking about at SC17. For more information on Intel Omni-Path Architecture, please visit http://intel.com/omnipath.
    1:11: More systems in the Top 500 than InfiniBand based on June 2017 Top500 List https://www.top500.org/list/2017/06/.
    1:18: Higher percentage of systems in Top100 compared to Infiniband EDR based on June 2017 Top500 List https://www.top500.org/list/2017/06/.
    2:01: Better price/performance than Infiniband: Configuration assumes a 750-node cluster, and number of switch chips required is based on a full bisectional bandwidth (FBB) Fat-Tree configuration. Intel® OPA uses one fully-populated 768-port director switch, and Mellanox EDR solution uses a combination of 648-port director switches and 36-port edge switches. Mellanox component pricing from www.kernelsoftware.com, with prices as of April 4, 2017. Compute node pricing based on Dell PowerEdge R730 server from www.dell.com, with prices as of April 4, 2017. Intel® OPA pricing based on pricing from www.kernelsoftware.com as of August 15, 2017 *Other names and brands may be claimed as property of others.
    11 min
  • Enabling AI Solutions for the Health and Life Sciences - Intel® Chip Chat episode 551
    Dr. Kyle Ambert, Senior Deep Learning Data Scientist at Intel Nervana, joins us to talk about enabling artificial intelligence solutions in the health and life sciences (HLS). Dr. Ambert's team uses machine learning and deep learning methods to solve real-world analytical problems, developing new prototypes and optimization strategies for deep learning networks for text analytics, natural language processing, and image recognition. In this interview, Dr. Ambert talks about his work to deliver AI solutions for doctors and clinicians, highlights important differences between deep learning and traditional machine learning methods, and discusses Intel's ecosystem of tools and technologies that are enabling AI. For more information on Dr. Ambert's work, please visit intelnervana.com.
    10 min
  • Next-gen Audio/Video Streaming Solutions from Surf Communications - Intel® Chip Chat episode 548
    Consumers expect real-time video that’s always on and viewable from anywhere. Niv Kagan, VP of Marketing at Surf Communications Solutions, describes how his company is using next-generation Intel® Xeon® Scalable Processors to enable their next-gen video and audio streaming solutions. With the increased video-scale transcoding performance of Intel’s new processors, there’s no need for solution providers to leverage discrete GPUs or customized hardware. End customers benefit from better solutions at lower cost, which means more and more innovative services are available every day. Visit surfsolutions.com for more information.
    8 min
  • Microsoft Coco Framework Eases Enterprise Blockchain Adoption - Intel® Chip Chat episode 546
    Christine Avanessians, Senior Manager of the Azure Blockchain Engineering team at Microsoft, joins us to talk about Microsoft’s new framework called Coco – a first-of-its-kind innovation that is accelerating enterprise readiness of blockchain. Blockchain, as explained by Christine, is a mechanism for secure multi-party computation that enables organizations to evolve business models and processes. Christine discusses how Microsoft is using Intel® Software Guard Extensions (Intel® SGX) to add scalability, privacy, and confidentiality to blockchain transactions. For more information on Microsoft and Intel’s work on blockchain and Coco, please visit http://azure.microsoft.com/blog.
    10 min

About Intel Chip Chat

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Intel Chip Chat is a recurring podcast series of informal interviews with some of the brightest minds in the industry, striving to bring listeners closer to the innovations and inspirations of the…