InvasIC Seminar: Vorträge im SFB/TRR 89 (HD 1280 - Video & Folien)

Prof. Philip Brisk (University of California, Riverside)

The last decade has seen significant advances in creating bedside monitoring algorithms for a host of medical conditions;however surprisingly few of these algorithms have seen deployment in wearable devices. The obvious difficulty is theavailability of computational resources on a device that is small enough to be convenient and unobtrusive. The computationalresource gap between conventional systems and wearable devices can be partly bridged by optimizing the algorithms(admissible pruning, early abandoning, indexing, etc.), but increasingly sophisticated monitoring algorithms have producedan arms race that is outpacing the performance and energy capabilities of the hardware community. Within this context,application- and domain-specialization are ultimately necessary in order to achieve the highest possible efficiency forwearable computing platforms.

Medical monitoring is a specialized form of time series data mining. Most time series data mining algorithms require similaritycomparisons as a subroutine, and there is increasing evidence that the Dynamic Time Warping (DTW) measure outperformsthe competition in most domains, including medical monitoring. In addition to medical monitoring, DTW has been used indiverse domains such as robotics, medicine, biometrics, music/speech processing, climatology, aviation, gesture recognition,user interfaces, industrial processing, cryptanalysis, mining of historical manuscripts, geology, astronomy, space exploration,wildlife monitoring, and many others. Despite its ubiquity, DTW remains too computationally intensive for use in real-timeapplications because its core is a dynamic programming algorithm that has a quadratic time complexity; however, recentalgorithmic optimizations have enabled DTW to achieve near-constant amortized time when processing time series databasescontaining trillions of elements.

As further software optimization appears unlikely to yield any further improvements, attention must be turned to hardwarespecialization. This talk will present the design, implementation, and evaluation of an application-specific processor whoseinstruction set has been customized to accelerate a software-optimized implementation of DTW. Compared to a 32-bitembedded processor, our design yields a 4.87x improvement in performance and a 78% reduction in energy consumptionwhen prototyped on a Xilinx EK-V6-ML605-G Virtex 6 FPGA.

Prof. Brett Meyer (McGill University, Canada)

Recently, the combination of semiconductor manufacturing technology scaling and pressure to reduce semiconductor systemcosts and power consumption has resulted in the development of computer systems responsible for executing a mix ofsafety-critical and non-critical tasks. However, such systems are poorly utilized if lockstep execution forces all processor coresto execute the same task even when not executing safety-critical tasks. Execution fingerprinting has emerged as analternative to n-modular redundancy for verifying redundant execution without requiring that all cores execute the same taskor even execute redundant tasks concurrently. Fingerprinting takes a bit stream characterizing the execution of a task andcompresses it into a single, fixed-width word or fingerprint.

Fingerprinting has several key advantages. First, it reduces redundancy-checking bandwidth by compressing changes toexternal state into a single, fixed-width word. Second, it reduces error detection latency by capturing and exposingintermediate operations on faulty data. Third, it naturally supports the design of mixed criticality systems by making dual-,triple-, and n-modular redundancy available without requiring significant architectural changes. Fourth, while it can’tguarantee perfect error detection, error detection probabilities and latencies can be tuned to a particular application.Together, these advantages translate to improved performance for mixed-criticality systems.

In this talk, I will describe fingerprinting in safety-critical systems and explore the various trade-offs inherent in itsapplication at the architectural level and choices related to fingerprinting subsystem design, including: (a) determining whatapplication data to compress, as a function of error detection probability and latency, and (b) identifying a correspondingfingerprinting circuit implementation.

Prof. Mitra (National University of Singapore)

Moore´s Law enables continued increase in the number of cores on chip; but power and thermal limits imply that a significantfraction of these cores have to be left switched off --- or dark --- at any point in time.This phenomenon, known as darksilicon, is driving the emergence of heterogeneous/asymmetric computing platforms consisting of cores with diverse power-performance characteristics enabling better match between the application requirements and the compute engine leading tosubstantially improved energy-efficiency. In this talk, we present the challenges and opportunities offered by static andadaptive heterogeneous multi-cores towards low-power, high-performance mobile computing.

For static asymmetric multi-cores, we present a comprehensive power management framework that can provide highperformance while minimizing energy consumption within the thermal design power budget. We then describe an adaptiveheterogeneous multi-core architecture, called Bahurupi, that can be tailored according to the application by software.Bahurupi is designed and fabricated as a homogeneous multi-core system containing identical simple cores. Post-fabrication,software can configure or compose together the primitive cores to create a heterogeneous multi-core that best matches theneeds of the currently executing application.

To meet required real-time constraints, modern embedded systems have to perform many tasks in parallel and therefore require the modeling of concurrent systems with an adequate notion of time. To this end, several models of computation (MoCs) have been defined that determine why (causality), when (time), which atomic action of the system is executed. The most important classes of MoCs are event-triggered, time/clock-triggered, and data-driven MoCs that have their on advantages and disadvantages. This talk gives an overview on the design flow used in the Averest system developed at the University of Kaiserslautern. The heart of this design flow is a synchronous (clock-driven) MoC which is used for modeling, simulation, and formal verification. The use of a synchronous MoC offers many advantages for these early design phases. For the synthesis, however, it is for some target architectures difficult to maintain the synchronous MoC, and therefore transformations are applied to translate the original models into other MoCs. In particular, we consider transformations that allow developers to desynchronize the system into asynchronous components which is a new technique to synthesize distributed/multithreaded systems from verified synchronous models.

To meet required real-time constraints, modern embedded systems have to perform many tasks in parallel and therefore require the modeling of concurrent systems with an adequate notion of time. To this end, several models of computation (MoCs) have been defined that determine why (causality), when (time), which atomic action of the system is executed. The most important classes of MoCs are event-triggered, time/clock-triggered, and data-driven MoCs that have their on advantages and disadvantages. This talk gives an overview on the design flow used in the Averest system developed at the University of Kaiserslautern. The heart of this design flow is a synchronous (clock-driven) MoC which is used for modeling, simulation, and formal verification. The use of a synchronous MoC offers many advantages for these early design phases. For the synthesis, however, it is for some target architectures difficult to maintain the synchronous MoC, and therefore transformations are applied to translate the original models into other MoCs. In particular, we consider transformations that allow developers to desynchronize the system into asynchronous components which is a new technique to synthesize distributed/multithreaded systems from verified synchronous models.