Semi Doped

As embedded flash hits a physical and economic scaling wall below 22nm, a new on-chip memory is needed. Ilan Sever of WeeBit Nano joins to explain how Resistive RAM (ReRAM) is positioned to become the new standard by offering a low-cost, high-endurance alternative. Ilan details how ReRAM's simple back-end-of-line integration, automotive qualification, and future applications in AI in-memory compute create a compelling replacement for the incumbent technology.

"In geometries below 28 or 22 nanometer, flash reached its physical limit, actually. So physically you cannot implement embedded flash anymore and the industry had been looking for alternative technologies for a few decades now."
— Ilan Sever, WeeBit Nano

Key Takeaways:

- The inflection point for on-chip memory is physical. Embedded flash cannot scale below the 28/22nm node because its floating gate becomes too small to reliably hold charge.

- The economic problem with eFlash is its 25-30% cost increase, a result of adding 8-10 extra masks to a standard CMOS process—a non-starter for cost-sensitive MCUs.

- ReRAM's manufacturing advantage is its simplicity. It's built in the back-end-of-line (BEOL) metal layers, adding only two masks and not interfering with the sensitive transistors below.

- The physics are different: ReRAM isn't storing charge, it's changing resistance by using voltage to form or dissolve a conductive filament of oxygen vacancies in a dielectric.

- Automotive qualification is the key market validation. WeeBit's ReRAM is qualified for the AEC-Q100 standard and demonstrates 100,000 write cycles—10x that of typical eFlash.

- The business model isn't just a recipe; it's a full IP module with the bit cell, analog circuits, digital logic, and programming algorithms, which is what SoC designers actually need.

- Beyond replacing flash, ReRAM (as a memristor) is a foundational technology for future in-memory compute (IMC) AI accelerators that perform calculations inside the memory to save power.

Chapters:
0:00 The Overlooked Memory
4:15 The eFlash Scaling Wall
6:03 Four Uses of NVM
23:19 The Cost of eFlash
27:29 Introducing ReRAM
32:25 How ReRAM Works
37:12 Fab-Friendly Materials
42:14 Automotive Qualification
44:30 The Vertically Integrated IP Model
51:13 Future: In-Memory Compute
54:19 Innovation Story: Self-Trimming

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Qualcomm re-entered the data center inference market late — competitive GPUs, XPUs, and custom accelerators are already out there. Durga Malladi (EVP/GM, Technology Planning, Edge & Data Center) explains why they didn't build another me-too accelerator and instead placed a differentiating technical bet: High Bandwidth Compute (HBC).

The difference between HBC and HBM: HBM is stacked DRAM that shuttles data across wide buses to a separate accelerator — very high bandwidth, but expensive and power-hungry. HBC bonds stacked DRAM directly on top of a custom logic die using wafer-on-wafer techniques, so a lot of the compute runs literally next to memory. The result is lower latency and lower power per bit — and 18x effective bandwidth on the AI 250 versus the AI 200 at the SAME 768 GB LPDDR capacity and the SAME 160 kW per rack.

Why the late-mover bet works: Qualcomm's differentiation isn't just architectural. Their foundry and memory-vendor relationships let them credibly promise the multi-megawatt-to-gigawatt supply hyperscalers need. Memory vendors are developing their own HBC-equivalent variants as partners rather than pure competitors, and Qualcomm expects the two technologies to co-evolve. Silicon is back in the lab; proof points land in Q1/Q2 2027.

Chapters:
0:00 Introduction
2:49 The Memory Wall Problem
8:05 HBC Physical Architecture
9:33 HBC vs. Custom HBM
11:50 Silicon Proof Points Coming
12:08 Managing Thermals
13:34 Dragonfly AI 250
14:48 Trillion-Parameter Model on One Card
16:56 Tokenomics and TCO
18:26 Why TCO is Key
19:26 Manufacturing at Scale

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The debate over "pacing" AI for safety is a red herring, as the practical outcome of more safety work is not a slowdown but a net increase in demand for compute hardware. Austin Lyons and Vik Sekar unpack Dario Amodei's call to slow down frontier AI development, arguing that the true governors on AI are not voluntary agreements but physical data center bottlenecks and geopolitical realities. They conclude that the push for more safety and interpretability will ultimately drive more sales of both training (GPUs) and inference (XPUs) hardware.

Today's sponsor is G2i — expert training data, evals, and RL environments for AI labs: https://fandf.co/4wZvKHS

Chapters:
0:00 Introduction: Pacing AI
1:36 Recapping Dario Amodei's Essay
7:42 Hot Take: Anthropic vs. OpenAI
11:34 The John Deere Playbook
15:22 The Problem with Interpretability
17:53 Pulling the Plug
19:03 The Real Bottleneck: Data Centers
22:03 The Geopolitical Blind Spot
23:41 Counter-narratives: Meta & Open Source
27:26 The Investment Thesis: Pacing Increases Compute
32:29 The Financial System Analogy
36:05 AI Safety as the New Cybersecurity

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The emergence of user-friendly AI agents is creating massive new hardware demand, which in turn is forcing the semiconductor industry into a complex, multi-year transition to High NA EUV lithography and an entirely new 12-inch photomask standard. Austin Lyons and Vik Sekar unpack the physics and economics of ASML's move to High NA, explaining why it necessitates a shift from 6-inch to 6x12-inch masks and what this means for the timelines of TSMC, Intel, and Samsung.

"This is where you have to get the whole supply chain coordinated around this. And this is why you really ultimately need ASML's biggest customers to stand up and say, 'We're going to buy this.'"
— Austin Lyons, Chipstrat

Key Takeaways:

- ASML's High NA EUV (0.55 NA) solves resolution but creates a new problem: anamorphic optics (4x by 8x demagnification) cut the exposure field in half, effectively doubling the cost per wafer.

- The industry's fix for High NA's halved output is a new 6x12-inch photomask standard — the 12-inch dimension compensates for the 8x demagnification, restoring the full 26mm x 33mm reticle size.

- This shift to 12-inch masks is a full supply chain problem, which is why TSMC is waiting until 2030 for high-volume manufacturing while the ecosystem matures over the next 5-7 years.

- Intel's aggressive first-mover strategy on High NA — with over 1 million wafers processed to date — is a direct reaction to its disastrous delay in adopting the previous generation of EUV.

- Nearly 30% of ASML's revenue comes from recurring services (€2.8B of €9B in Q2), giving it a more stable financial profile than a typical equipment manufacturer.

- The new wave of AI agents (Astra, Muse, Instinct) is moving from simple instruction-following to proactive partnership, creating hundreds of millions of new users for server CPUs and memory.

- Integrating AI agents into ubiquitous text platforms like WhatsApp is key for mass adoption, as it solves the 'blank text box problem' for non-technical users who can simply text a request.

Chapters:
0:00 Episode Opening
2:23 The Rise of AI Agents
6:00 Instinct: The Autonomous Agent
10:50 Productizing AI for Mass Adoption
14:03 From AI Agents to ASML
24:29 The Photomask Stitching Problem
31:49 High NA's Anamorphic Optics Tradeoff
36:39 The Cost of a Halved Reticle
37:26 The 6x12-Inch Mask Solution
39:08 A Full Supply Chain Problem
41:17 TSMC, Samsung & Intel Timelines
48:24 Intel's EUV History Lesson

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Austin and Vik react to OpenAI's Jalapeño announcement at Hot Chips. Plus extra spicy questions like should OpenAI sell it, how much of this was AI-written RTL, and where is Anthropic's chip?

Key Takeaways:

- The chip's core design philosophy is "dark silicon is cheaper than idle accelerators" — using one balanced chip and power-gating unused blocks is more efficient than a two-chip (e.g. GPU + LPU) solution.

- The unprecedented nine-month RTL-to-tapeout cycle was enabled by AI for EDA tools, serving as a wake-up call that small, expert teams can now develop Rubin-class chips in under a year.

- Jalapeño's key innovation is a NUMA-style architecture that gives each accelerator a local HBM slice, solving the memory contention that throttles performance in unified memory systems.

- OpenAI chose Broadcom's ESUN for its scale-up network to connect 128 chips in the rack at 600 GB/s and up to 2,048 chips across 16 racks at 200G --- all scale up!

- The design's "regret factor" principle justifies generality — the opportunity cost of being unable to support a future model is far higher than the marginal cost of adding hardware flexibility upfront.

Chapters:
0:00 Hot Chips Reaction
2:32 Designing for User Experience
11:16 A Generalized Inference Chip
14:18 The Foundry-IDM Analogy
18:42 The 'Regret Factor'
21:02 The 9-Month Design Cycle
23:45 Challenging the Two-Chip Solution
35:08 Solving HBM Underutilization
36:46 The NUMA Architecture Solution
39:28 System-Level ESUN Networking
42:06 Dark Silicon vs. Idle Accelerators
49:08 A Wake-Up Call for the Industry
52:59 Where's Anthropic's Chip?

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The rise of user-friendly agentic AI platforms will create a massive new demand category for dedicated, high-core-count "agentic CPUs" to execute tasks in parallel, fundamentally reshaping the server CPU market beyond just feeding GPUs.

Key Takeaways:

- The 'Mac Mini Craze' wasn't about having a GPU on your desk — it was also about security, as users needed a sandboxed machine to run untrusted agent code like OpenClaw, a problem cloud VMs solve too.

- In AI servers, the GPU is the 'genius' doing the thinking, while the host CPU is the 'assistant' whose primary job is keeping the GPU fed, requiring high single-core performance.

- Agentic tasks create a 'spillover' of parallel work that overwhelms the host CPU, creating a new demand category for dedicated, high-core-count 'agentic CPUs' in separate racks.

- The procurement decision for agentic CPUs becomes about cost-per-core, or 'cost per employee' — balancing core count (like AMD's 256-core chips) against single-core speed.

- Intel's P-rack (Performance) and E-rack (Efficiency) offerings are a direct response to this need for heterogeneous CPU solutions tailored to different agentic workloads.

- The mass adoption of agentic AI could create demand for a billion new CPU cores in the cloud, driven by the convenience of 'easy button' platforms over self-hosting.

- A key bottleneck to this heterogeneous future is the orchestration software needed to schedule jobs across different CPUs and accelerators from multiple vendors.

Chapters:
0:00 Introducing Grok bot
3:45 Grok bot's Cloud VM Architecture
6:28 The 'Mac Mini Craze' Explained
14:38 Three CPU Deployment Models
16:02 GPU as Genius, CPU as Assistant
21:36 The Limits of the Host CPU
25:20 The 'Office Building' Analogy
29:09 Cost-Per-Core is the Metric
31:20 Intel's P-rack and E-rack
37:32 The Orchestration Bottleneck
40:19 Where Grok bot's VM Lives
44:22 The Unanswered Question

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Tensordyne co-founder and CPO R K Anand joins Austin to discuss the company's strategy for disrupting AI inference. RK explains how Tensordyne combines power-efficient logarithmic math with a battle-hardened networking fabric from partner HPE Juniper. The result is a high-density, air-cooled system designed to efficiently run massive Mixture-of-Experts models in existing data centers.

Key Takeaways:
- The core innovation isn't just log math, it's the patented method for accumulation. This turns expensive multiplications into cheap additions, freeing die space for a massive on-chip SRAM cache.

- Networking is a partnership, not a project. Tensordyne leverages HPE Juniper's 7th-gen router fabric, skipping development cycles to get a 1-2 microsecond latency solution ideal for random MoE traffic.

- The power and density claims are radical. By combining log math silicon with an air-cooled fabric, Tensordyne packs 72 chips into a 13U chassis at just 30 kW — a quarter of the space and power of an NVL72.

- One go-to-market advantage is air cooling. The 30 kW, 19-inch rack system can be deployed in existing 'brownfield' enterprise and telco data centers that cannot support liquid cooling.

- Partnerships de-risk the aggressive timeline. Broadcom provides access to TSMC 3nm and HBM, while strategic investor HPE Juniper provides the carrier-grade fabric with 'five nines' reliability.

Chapters:
0:00 Introducing Tensordyne
5:32 The Juniper vs. Cisco Playbook
11:29 Origin Story: Automotive Power Constraints
15:37 The Secret Sauce of Log Math
18:02 Pivoting to the Data Center
22:08 Leveraging a Router Backplane for AI
27:22 Why Router Fabrics Suit MoE Models
34:12 The Three Phases of Inference Hardware
37:40 How One Chip Handles Pre-fill & Decode
40:34 The 'Too Good to Be True' System Specs
43:31 Go-to-Market: The Air-Cooled Advantage
48:21 De-risking with Strategic Partnerships
52:37 Solving the Software Problem with AI

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- The software moat is eroding. Tensordyne argues that modern agentic AI workflows can now automate the generation of optimized software kernels, solving the classic adoption problem for new hardware.

Austin Lyons and Vik Sekar break down three stories that hit semis last week. They analyze a proposed US ban on Chinese optical transceivers that threatens to cut off 50% of the global supply, the market's reaction to AMD's surprise $800M CapEx spend despite strong earnings, and how a new company called Volta Infrastructure landed a $10B compute deal with Anthropic by pioneering a new financial model for AI.

Key Takeaways:

- The proposed ban on Chinese optical transceivers is based on a flawed security rationale—the components are simple signal converters, not a meaningful vector for malware.

- A ban would be self-defeating, as it would cut off the ~50% of global transceiver supply assembled in China, creating the very data center disruption it claims to prevent.

- AMD's successful pivot to a data-center-first company (58% of revenue) is being scrutinized for its high CapEx—$800M vs an expected $200-300M—revealing the hidden costs of securing supply.

- Nvidia's use of on-chip SRAM for inference's decode phase highlights a strategic gap for AMD, which lacks a compelling SRAM-based solution to compete on disaggregated workloads.

- Volta Infrastructure's $10B deal with Anthropic is an innovation in finance, not tech; it applies low-cost 'infrastructure debt' to AI compute by framing clusters as predictable 'token factories'.

- The Volta deal was necessary because all existing CSP capacity is allocated; it acts as a 'clean balance sheet' SPV to secure low-cost debt for Anthropic's new, dedicated Nvidia capacity.

Chapters:
0:00 Intro: News Take Format
0:40 The China Optical Ban
4:02 A Flawed Security Rationale
11:30 Market & Supply Chain Impact
15:07 Investment Paralysis
15:52 AMD's Earnings Scrutiny
24:46 AMD's Missing SRAM Strategy
25:33 Volta's $10B Anthropic Deal
28:55 Volta's 'Toll Road' Model
32:19 Why the Volta Deal Was Necessary
33:38 The 'One Customer' Counterpoint
34:27 Wrap: Tech & Financial Innovation

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The physical limits of copper are forcing a shift to optical interconnects in AI data centers. Austin sits down with GlobalFoundries' Thomas Barber to unpack why GF thinks it can lead that transition twice over: once with its long-running silicon photonics platform, and again with the specialty Silicon Germanium process the industry needs to drive it.

"The enemy to me right now is copper. I'm trying to beat copper, right? If TSMC wins and we win, that's great because we're both displacing copper. And until all the copper is gone, there's plenty of market to go around."
— Thomas Barber, GlobalFoundries

Key Takeaways:
- Copper's usable range halves every time the data rate doubles, and 200 Gbps/lane inside a rack-scale AI cluster is already past the point copper can handle.

- CPO's real win isn't speed, it's power: saving 20-25 pJ/bit frees part of a data center's fixed 50-100 MW budget to go toward compute instead of moving bits.

- GlobalFoundries leads photonics revenue for an unglamorous reason: it moved to 300mm wafers early, which yields 2.25x more die per wafer than the 200mm lines rivals still run.

- CPO can end up more reliable than the pluggables it's replacing, not less, because it deletes the physical plug connector, and dust at that connector is the leading cause of field failures.

- The OCI MSA picks NRZ over faster PAM4, deliberately going wide and slow, because NRZ's native bit error rate is a million times lower, which simplifies the receiver and cuts power.

- GlobalFoundries stacks two specialty processes into one edge: micro-mirror couplers on the photonic side, and Silicon Germanium transistors hitting 350-400 GHz on the electrical side driving them.

- The real competitor for silicon photonics isn't another foundry, it's copper itself — and that market is big enough that GlobalFoundries and TSMC can both win without taking share from each other.

Chapters:
0:00 GlobalFoundries in Photonics
1:21 GF's Photonics Strategy
3:02 GF's Market Leadership
5:06 300mm Wafer Advantage
6:55 Copper's Range Limits
9:18 Pluggable to CPO
13:48 CPO Reliability
19:22 OCI MSA Explained
26:20 GF's Scale Platform
29:04 Micro Mirror Technology
31:32 Photonics vs. Copper
38:25 Silicon Germanium Advantage

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A retimer is a small, unglamorous chip. Astera turned it into a high-margin franchise. Austin and Vik cover why copper gives up at PCIe speeds, what a retimer does that a redriver can't, and how one H100 socket became a moat. Then Scorpio: can Astera take switch share from Broadcom?

Key Takeaways:
- 30cm of PCB trace at Gen 5's 32 GT/s and the signal is gone. Signal integrity is an inside-the-server problem, not just a rack-to-rack one.
- Gen 6 swaps NRZ for PAM4. Four voltage levels instead of two — a third the eye height, ~9.5 dB of SNR gone.
- A redriver amplifies, noise included. A retimer recovers the clock and data, rebuilds the signal, and resets the jitter budget.
- Astera won H100 by shipping PCIe 5 retimers at volume first, then bundling COSMOS on top. The chip became a fleet telemetry sensor.
- Sticky socket: H100 carried straight into an Aries 6 design-in on Blackwell.
- Scorpio moves up the stack. Same signal conditioning IP, higher ASP, pointed at Broadcom's PCIe switch business.
- Astera granted Amazon a warrant — 3.26M shares at $142.82, vesting against up to $6.5B of purchases through 2033. Equity flowing to the customer, and it sizes the Scorpio P-Series commitment behind Trainium 2 and 3.

Chapters:
0:00 The Astera Labs Franchise
3:32 The PCIe Copper Problem
6:53 Signal Smearing and Jitter
11:52 Eye Diagrams Explained
14:59 Equalization: Fixing the Signal
23:52 Redriver vs. Retimer
29:30 How Astera Won Nvidia
35:22 The Blackwell Scare
38:50 Scorpio: Moving into Switches
42:52 The UALink vs. Ethernet Battle
45:58 Taurus and Leo Product Lines

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