Co-packaged optics could change how AI data centers move enormous amounts of data—but 224G PAM4 is exposing the limits of long electrical interconnects.

Here's why copper's efficient reach is shrinking, how silicon photonics changes the architecture, and why packaging may become the next bottleneck.

At 224G PAM4, high-speed electrical interconnect design gets increasingly difficult.

Copper isn't suddenly obsolete. Engineers continue extending its capabilities with lower-loss laminates, better stackups, shorter channels, improved via structures, equalization, DSP, and increasingly sophisticated SerDes.

But the physics doesn't disappear.

Skin effect and dielectric loss increase with frequency, forcing tighter channel budgets as data rates rise. In one representative example discussed in the article, a 60 mm low-loss channel that stays below 10 dB insertion loss at 28 GHz for 112G can reach approximately 18–20 dB at 56 GHz when moving toward 224G.

And recovering increasingly degraded electrical signals costs power.

That's where silicon photonics and co-packaged optics (CPO) enter the architecture.

Instead of driving the high-speed electrical signal across a long PCB path to a faceplate optical module, CPO places the photonic engine adjacent to the switch ASIC, shortening the electrical path before converting the signal to light.

But photonics introduces its own manufacturing problems.

In this episode, we break down:

224G PAM4 channel loss and signal integrity

SerDes power and equalization

Silicon photonics and photonic integrated circuits

Co-packaged optics architecture

Wavelength-division multiplexing (WDM)

Fiber-to-chip optical coupling

Micron-scale alignment tolerances

External laser sources and reliability

Advanced photonics packaging

Manufacturing yield and test

Copper vs. pluggable optics vs. CPO

What 448G could mean for the next interconnect generation

The central engineering question isn't whether light is "better" than copper.

It's where electro-optical conversion should happen, how much power the interconnect consumes, and whether the resulting optical package can be manufactured reliably at hyperscale volumes.

That's why one of the most important CPO metrics to watch may not be another bandwidth number.

It's optical coupling yield at production volume.

READ THE FULL TECHNICAL ARTICLE:

Co-Packaged Optics: Improving the 224G Bottleneck in AI Data Centers

EXPLORE SILICON TO SOFTWARE:

Silicon to Software

FOLLOW SILICON TO SOFTWARE:

X: @SiToSoftware

Instagram: @silicon_to_software

Subscribe to Silicon to Software for engineering-focused analysis of PCB manufacturing, semiconductor technology, advanced packaging, AI hardware, signal integrity, and the physical infrastructure behind modern computing.

#CoPackagedOptics #SiliconPhotonics #AIDataCenters

Advanced packaging and chiplets are reshaping AI chips—but manufacturing the package may be harder than building the silicon.

Here’s why substrates, 2.5D and 3D packaging, yield, warpage, and capacity could determine which next-generation AI hardware actually ships.

As semiconductor scaling becomes increasingly difficult and expensive, chiplets have emerged as one of the industry’s most important architectural strategies. Instead of manufacturing one enormous monolithic die, engineers can divide a system into smaller dies and reconnect them using advanced semiconductor packaging.

But that doesn’t eliminate the manufacturing problem. It moves part of it.

In this episode of Silicon to Software, we break down the engineering behind chiplets and advanced packaging—and why substrate capacity, interposer manufacturing, thermal expansion, registration tolerance, bonding, and package yield have become critical constraints for AI accelerators and high-performance computing.

We cover:

• Why monolithic semiconductor scaling runs into reticle and yield constraints

• How chiplets change semiconductor manufacturing economics

• The manufacturing differences between 2.5D packaging and 3D packaging

• Silicon interposers, RDL, microbumps, TSVs, and hybrid bonding

• Why CTE mismatch creates warpage and reliability problems

• How ABF and other IC substrates affect advanced package manufacturability

• Why multi-die package yield is multiplicative

• The importance of known-good-die testing

• Why chiplets are not automatically cheaper than monolithic designs

• How advanced packaging capacity can constrain AI chip production

• The role of OSATs and substrate manufacturers

• How UCIe enables standardized die-to-die communication

• Why chip-package co-design and DFM need to begin before the floorplan is frozen

For engineering teams, the practical lesson is increasingly difficult to ignore: packaging can no longer be treated as something that happens after the chip is designed.

For advanced AI hardware, the package itself has become part of the system architecture.

[Insert Timestamps here]

READ THE FULL TECHNICAL ARTICLE:

https://www.silicontosoftware.com/chiplets-and-advanced-packaging/

EXPLORE SILICON TO SOFTWARE:

https://www.silicontosoftware.com/

Subscribe to Silicon to Software for engineering-focused analysis of AI hardware, semiconductor manufacturing, advanced packaging, PCB technology, electronics manufacturing, cybersecurity, and the infrastructure behind modern computing.

#AdvancedPackaging #Chiplets #Semiconductors

TSMC Arizona is becoming a $265B semiconductor manufacturing powerhouse—but the AI chip bottleneck isn't just inside the wafer fab.

CoWoS advanced packaging, HBM integration, IC substrates and ABF supply could determine how quickly the next generation of AI hardware actually ships.

TSMC's massive Arizona expansion is one of the largest semiconductor manufacturing investments ever undertaken in the United States. But focusing only on fabs misses an important part of the AI hardware supply chain.

In this episode of Silicon to Software, Imran Valiani breaks down the manufacturing layers underneath today's AI accelerator boom—from leading-edge wafer fabrication to CoWoS advanced packaging and the high-performance substrates underneath the package.

TSMC's Arizona commitment has expanded to a reported $265 billion, encompassing ten planned fabrication plants, two advanced-packaging facilities and an R&D center. At the same time, CoWoS capacity has remained extremely tight as demand for AI accelerators continues to push the advanced-packaging ecosystem.

We examine why simply increasing wafer capacity doesn't automatically increase finished AI accelerator output.

You'll learn about:

TSMC Arizona and the expansion of U.S. semiconductor manufacturing

Why CoWoS advanced packaging has become critical to AI accelerator production

How GPU-class processors integrate compute dies and HBM memory

Why IC substrates are a separate manufacturing constraint

The role of ABF (Ajinomoto Build-up Film) in high-performance packages

Why substrate supplier concentration creates supply-chain exposure

How CTE mismatch, package warpage and thermal cycling affect manufacturing yield

Why supplier qualification and yield learning can take months or longer

What the 2021–2022 ABF shortage revealed about hidden semiconductor dependencies

Why semiconductor reshoring requires more than simply constructing wafer fabs

For hardware engineers and sourcing teams, the broader lesson is important:

Wafer capacity is not the same thing as finished-device capacity.

A high-yield wafer still has to move through packaging, integration, substrate assembly, qualification, inspection and test before it becomes a usable AI accelerator. Those manufacturing layers operate on their own capacity and yield curves.

READ THE FULL TECHNICAL ANALYSIS

TSMC Arizona: The AI Chip Bottleneck Fabs Can't Fix

SILICON TO SOFTWARE

Engineering analysis covering semiconductor manufacturing, PCB technology, AI hardware, advanced packaging, electronics manufacturing, autonomous systems, and the physical infrastructure behind modern computing.

Silicon to Software

Follow Silicon to Software:

X: @SiToSoftware

Instagram: @silicon_to_software

LinkedIn: [INSERT LINK]

Subscribe to Silicon to Software for engineering-focused breakdowns of the hardware layer behind AI and emerging technology.

#TSMC #Semiconductors #AIChips

Autonomous cargo ships are already carrying real freight—but AI alone can't safely operate a ship.

Here's the hardware behind autonomous shipping: radar, LiDAR, edge computing, embedded systems, cybersecurity, and redundant controls.

Autonomous cargo ships are moving from experimental technology toward real commercial operation. But making a ship autonomous involves far more than installing an AI navigation system.

In this episode of Silicon to Software, host Imran Valiani examines the engineering behind autonomous shipping and the physical systems required to keep a vessel operating when sensors, communications, electronics, or software don't behave as expected.

We use the Yara Birkeland, an electric autonomous-capable container vessel operating in Norway, as a real-world reference point for understanding the technology stack. The vessel combines multiple navigation and control technologies while progressively moving toward reduced onboard crewing.

What you'll learn

Sensor Fusion & Autonomous Navigation

Radar, LiDAR, AIS, machine-vision cameras, and infrared imaging give autonomous vessels multiple ways to observe their environment.

But more sensors don't automatically mean more safety.

Rain, sea spray, visibility conditions, and positioning problems can affect multiple sensing systems simultaneously. That creates correlated failure modes engineers must account for when designing autonomous navigation systems.

Edge Computing & Embedded Systems

Autonomous vessels can't send every safety-critical decision to the cloud.

Sensor processing and time-critical navigation must happen onboard. Safety-critical steering and propulsion also introduce a fundamental architectural question: how do you separate AI perception workloads from deterministic control systems?

That distinction becomes critical when communications degrade or disappear.

Marine Electronics & Reliability

Shipboard electronics operate in an environment dominated by:

Salt and humidity

Vibration

Temperature cycling

Condensation

Corrosion

Long service lives

Those conditions influence PCB protection, conformal coating, connectors, mechanical mounting, enclosures, EMC testing, and equipment qualification.

Maritime Cybersecurity

Connecting navigation and control systems creates another engineering problem: attack surface.

GNSS spoofing, manipulated AIS information, compromised software updates, remote credentials, and supply-chain vulnerabilities can all affect autonomous systems.

Hardware roots of trust, secure boot, signed updates, network segmentation, and resilient system architecture therefore become part of the safety discussion—not simply an IT concern.

Redundancy & Failure Domains

Two systems aren't necessarily redundant simply because there are two of them.

If they share the same power bus, cooling system, network, controller, or physical compartment, one common-mode failure may still disable both.

True redundancy requires independent failure paths, a principle that extends well beyond ships into aerospace, automotive, robotics, industrial automation, and other safety-critical embedded systems.

Read the Full Technical Article

Autonomous Cargo Ships: How AI, Embedded Systems, and Sensors Could Transform Global Shipping

About Silicon to Software

Silicon to Software examines the physical engineering layer behind modern technology—from PCB manufacturing and semiconductor hardware to embedded systems, AI infrastructure, autonomous systems, cybersecurity, and electronics reliability.

Hosted by Imran Valiani, with 20+ years of experience in PCB manufacturing and technology sales.

X: @SiToSoftware

Subscribe to Silicon to Software for engineering discussions

#AutonomousShips #EmbeddedSystems #MaritimeTechnology

Smart glasses could eventually replace smartphones—but batteries, heat, optics, and packaging still stand in the way.

We break down the real engineering behind AI glasses, from optical waveguides and edge AI processors to thermal management and semiconductor packaging.

Smart glasses have been positioned as the next major computing platform for more than a decade. Today's hardware is significantly more capable—but building glasses that can replace a smartphone requires solving several tightly coupled engineering problems.

In this episode of Silicon to Software, Imran Valiani examines what happens beneath the frame.

We break down:

• BATTERY CAPACITY

Why increasing battery capacity affects temple thickness, weight distribution, thermal behavior, and the space available for every other subsystem.

• OPTICAL WAVEGUIDES

Why field of view, eyebox, brightness, optical efficiency, color control, manufacturing yield, and cost cannot be optimized independently.

• THERMAL MANAGEMENT

Why cameras, radios, displays, and AI processors operating close to the user's skin create a fundamentally different thermal problem from smartphones and laptops.

• EDGE AI PROCESSORS

How smaller AI processors and quantized models are bringing inference onto wearable hardware—and why model capability still has to fit inside strict memory, energy, and thermal budgets.

• ANTENNAS + SENSORS

Why RF clearance, camera placement, microphones, speakers, batteries, processors, and mechanical structures compete for the same limited internal volume.

• SEMICONDUCTOR PACKAGING

Why shrinking processors, memory, radios, and sensor electronics isn't enough. Integration density, thermal performance, assembly precision, manufacturing yield, and reliability ultimately determine whether a prototype can scale.

The central engineering problem is systems integration.

Improving one subsystem can create a new constraint somewhere else.

That's why the path from impressive smart-glasses demo to an all-day computing platform depends on coordinated advances across AI hardware, embedded systems, optical engineering, battery technology, RF design, thermal management, semiconductor packaging, and electronics manufacturing.

READ THE FULL ARTICLE:

https://www.silicontosoftware.com/smart-glasses-hardware-not-ready/

SILICON TO SOFTWARE:

https://www.silicontosoftware.com/

CONNECT:

LinkedIn: [INSERT LINK]

X: @SiToSoftware

Instagram: @silicon_to_software

Subscribe for engineering-first analysis of the physical hardware behind AI, semiconductors, PCB technology, embedded systems, autonomous systems, and next-generation computing.

#SmartGlasses #AIHardware #HardwareEngineering

AI data center cooling is becoming a physical limit on AI growth as next-generation GPU racks push toward 142kW of power. Why can't conventional air cooling keep up — and can liquid cooling solve the thermal problem?

In this episode of Silicon to Software, Imran Valiani examines the engineering problem hiding underneath the AI infrastructure boom: getting enormous amounts of heat out of increasingly dense GPU systems.

NVIDIA's GPU power trajectory illustrates what's happening.

H100 reaches up to 700W in its SXM configuration. B200 reaches up to 1,000W in the HGX B200 configuration. Blackwell Ultra pushes the maximum envelope to 1,400W per GPU in the mandatory-liquid-cooled GB300 NVL72 rack architecture.

A complete GB300 NVL72 rack can require up to 142kW.

Nearly all of that electrical energy ultimately becomes heat that has to be removed from the equipment and rejected by the facility.

That's where the AI scaling problem gets physical.

In this episode, we break down:

• Why thermal flux matters as much as total GPU power
• Why conventional air cooling struggles with 100kW+ AI racks
• Direct-to-chip liquid cooling and cold plates
• Coolant Distribution Units (CDUs) and facility cooling loops
• Single-phase and two-phase immersion cooling
• Thermal interface materials and thermal resistance
• High-density GPU rack power delivery
• Water consumption and data center cooling
• Reliability, plumbing and maintenance challenges
• Why power and cooling can delay AI infrastructure deployment

The bigger engineering question isn't simply who can manufacture the fastest AI accelerator.

It's who can actually power and cool thousands of them at scale.

A GPU that cannot reject its heat will eventually throttle. And a throttled accelerator doesn't deliver the compute performance the facility paid for.

That makes thermal management, liquid cooling, power distribution and data center infrastructure fundamental parts of the AI hardware roadmap.

[Insert Timestamps here]

━━━━━━━━━━━━━━━━━━━━

READ THE FULL TECHNICAL ARTICLE:

https://www.silicontosoftware.com/ai-data-center-cooling-bottleneck/

EXPLORE SILICON TO SOFTWARE:

https://www.silicontosoftware.com/

━━━━━━━━━━━━━━━━━━━━

FOLLOW SILICON TO SOFTWARE:

X: @SiToSoftware Instagram: @silicon_to_software

Subscribe to Silicon to Software for engineering-focused discussions covering AI hardware, PCB manufacturing, semiconductors, advanced packaging, data center infrastructure and the physical systems behind modern computing.

#AIDataCenters #LiquidCooling #AIHardware

Solid-state batteries promise to transform EVs. So why aren't they already powering millions of electric cars? The biggest obstacle may not be the battery chemistry anymore—it's manufacturing them reliably at automotive scale.

Solid-state batteries could deliver higher energy density, improved safety, faster charging, and potentially longer life than today's conventional lithium-ion EV batteries.

But there's a massive difference between building a battery cell in a laboratory and manufacturing tens of thousands of identical, automotive-grade cells every day.

In this episode of Silicon to Software, Imran Valiani examines the engineering and manufacturing challenges keeping solid-state battery technology from reaching mass-market electric vehicles.

We break down the lithium dendrite problem and how microscopic lithium-metal growth can penetrate a solid electrolyte and create an internal short circuit.

Then there's an equally important challenge: the electrode-electrolyte interface. Unlike a liquid electrolyte, a solid material can't simply flow into microscopic gaps. Maintaining intimate contact between solid surfaces through charging cycles, mechanical movement, expansion, contraction, and temperature changes becomes a serious engineering problem.

And that's before reaching the factory.

We examine the manufacturing problems involving:

• Stack pressure and mechanical contact
• Solid-electrolyte material consistency
• Moisture and contamination control
• Dry-coating and thin-film manufacturing
• Production throughput
• Automotive-grade manufacturing yield
• Cost per kilowatt-hour
• Scaling from laboratory cells to gigafactory production

We'll also look at what companies such as Toyota and QuantumScape can tell us about the industry's progress—and why production announcements matter more than another impressive laboratory demonstration.

Solid-state batteries aren't vaporware.

The technology is real.

But getting from “it works” to “we can manufacture it reliably millions of times” is one of the hardest transitions in hardware.

And that's the part most battery headlines leave out.

READ THE FULL ARTICLE

For the detailed engineering analysis, sources, and additional technical context:

Solid-State Batteries Explained | Silicon to Software

FOLLOW SILICON TO SOFTWARE

Website: Silicon to Software

X: @SiToSoftware

Subscribe to Silicon to Software for engineering-focused discussions about semiconductors, PCB manufacturing, AI hardware, automotive electronics, energy technology, and the physical infrastructure behind modern technology.

#SolidStateBatteries #EVTechnology #BatteryTechnology

Counterfeit semiconductor chips can look genuine, pass basic testing, and still create serious reliability risks inside real electronics. Here's how fake ICs enter the semiconductor supply chain—and how engineers actually detect them.

Counterfeit chips aren't always crude copies.

Some are genuine semiconductor components recovered from discarded electronics, cleaned, resurfaced, remarked, and sold as new. Others can involve substituted devices, unauthorized production, defective components, or falsified traceability documentation.

In this episode of Silicon to Software, Imran Valiani draws on more than 20 years in PCB electronics manufacturing and technology sales to examine the engineering reality behind counterfeit semiconductor components.

We break down how suspect parts can move through gray-market semiconductor supply chains, why multiple broker transactions can destroy component traceability, and why an IC that passes a basic room-temperature functional test isn't necessarily proven reliable for long-term deployment.

You'll also learn how engineers and electronics manufacturers use techniques including X-ray inspection, computed tomography, Scanning Acoustic Microscopy (SAM), XRF analysis, decapsulation, electrical characterization, and known-good reference comparisons to investigate suspect components. No single technique detects every counterfeit type, which is why authentication depends on layered inspection and supply-chain controls.

We also examine why counterfeit semiconductor risk matters across:

• AI hardware and data centers • Automotive electronics • Defense and aerospace systems • Medical devices • Industrial electronics • PCB and electronics manufacturing

And there's an important manufacturing issue that often gets overlooked: recycled components can arrive with an unknown history of thermal cycling, moisture exposure, storage, handling, and previous reflow, making component authenticity a reliability and assembly-quality issue—not merely a procurement problem.

In this episode:

• What actually qualifies as a counterfeit semiconductor • How recycled and remarked ICs enter legitimate electronics • How gray-market sourcing creates traceability gaps • Why visual inspection alone isn't enough • Why basic functional testing has blind spots • How X-ray, SAM, XRF, and decapsulation work • Why counterfeit detection varies by component and counterfeit type • The risks for AI hardware, automotive, defense, and medical electronics • How supplier qualification and traceability reduce exposure • Why component authenticity follows a product all the way from procurement to field reliability

Counterfeit Semiconductor Chips Explained: How Fake ICs Enter Electronic Devices and Why They're So Hard to Detect

About Silicon to Software

Silicon to Software explores the hardware layer behind modern technology—from PCB design and electronics manufacturing to semiconductor engineering, advanced packaging, AI infrastructure, reliability, embedded systems, and emerging technologies.

Hosted by Imran Valiani Sales Director, PCB Electronics Manufacturing 20+ years serving Bay Area and global technology companies.

Follow Silicon to Software

Website: Silicon to Software X: @SiToSoftware

#CounterfeitChips #Semiconductors #HardwareEngineering

AI's energy crisis is becoming a hardware problem. Could neuromorphic chips help AI scale without consuming enormous amounts of electricity?

Discover how brain-inspired computing, spiking neural networks, Intel Loihi 2, IBM NorthPole, and other emerging AI hardware could change the future of energy-efficient computing.

Artificial intelligence is scaling at an extraordinary pace—but the electricity and infrastructure required to power it are scaling too.

In this episode of Silicon to Software, Imran Valiani explores the engineering behind neuromorphic computing and why researchers are designing processors inspired by the human brain.

The human brain operates on roughly 20 watts. Modern AI infrastructure can require massive data centers packed with GPUs, high-bandwidth memory, cooling systems, and power-delivery infrastructure.

So what makes biological computing so efficient?

We break down:

• Why AI workloads consume so much electricity • The "memory wall" limiting conventional computing architectures • How spiking neural networks (SNNs) work • Why event-driven computing can reduce unnecessary computation • Intel's Loihi 2 neuromorphic processor • The 1.15-billion-neuron Hala Point system • IBM NorthPole and compute-near-memory architecture • BrainChip Akida and edge AI • Why neuromorphic hardware can deliver major efficiency advantages on certain workloads • Why today's transformer-based LLMs can't simply be moved onto neuromorphic processors • Where brain-inspired computing could realistically make an impact

Neuromorphic computing isn't about replacing GPUs tomorrow.

It's about asking a much bigger engineering question:

How do we continue scaling artificial intelligence when electricity, cooling, memory bandwidth, and data-center infrastructure become hard physical constraints?

━━━━━━━━━━━━━━━━━━

🌐 READ THE FULL ARTICLE

Silicon to Software: https://www.silicontosoftware.com/neuromorphic-chips-ai-energy-crisis/

━━━━━━━━━━━━━━━━━━

🔗 FOLLOW SILICON TO SOFTWARE

Website: https://www.silicontosoftware.com/

X: @SiToSoftware

Instagram: @silicon_to_software

Subscribe to Silicon to Software for engineering-focused discussions on AI hardware, semiconductor technology, PCB engineering, advanced computing, electronics manufacturing, and the physical infrastructure behind modern technology.

#NeuromorphicComputing #AIHardware #ArtificialIntelligence

Smart city hardware is quietly turning modern cities into giant distributed computers. But what actually sits behind the AI cameras, IoT sensors, 5G networks and intelligent infrastructure?

In this episode of Silicon to Software, Imran Valiani breaks down the six physical hardware layers making smart cities possible—from sensors buried beneath roads to edge AI computers operating inside traffic cabinets.

We go beyond the apps and dashboards to examine the engineering underneath the smart city.

You'll discover:

• How IoT sensors monitor traffic, parking, air quality, water systems and urban infrastructure • Why LoRaWAN and NB-IoT make massive sensor deployments practical • How AI-powered cameras perform inference directly at the edge • Why edge computing matters when milliseconds count • How 5G, RedCap and fiber work together across urban networks • Why smart streetlights are becoming IoT infrastructure hubs • What IPC-6012 Class 3, conformal coating and environmental protection mean for outdoor PCB reliability • How city operations centers aggregate massive amounts of infrastructure data • Why OT cybersecurity requires a different threat model from enterprise IT • How Zero Trust, SBOM requirements and post-quantum cryptography are beginning to influence next-generation infrastructure

A modern smart city isn't simply "connected."

It's a distributed computing system.

Sensors become its inputs. Edge computers become local processors. Fiber and 5G become the communications fabric. Data centers become the aggregation layer.

And underneath all of it is physical hardware that has to survive years of heat, moisture, vibration, cybersecurity threats and continuous operation.

────────────────────

READ THE FULL ARTICLE:

Smart City Hardware Explained: 6 Layers Turning Cities Into Computers SiliconToSoftware.com/smart-city-hardware-explained/

────────────────────

ABOUT SILICON TO SOFTWARE:

Silicon to Software explores the engineering behind AI hardware, PCB design and manufacturing, semiconductors, embedded systems, advanced computing, cybersecurity and the infrastructure powering modern technology.

Hosted by Imran Valiani, a PCB electronics manufacturing and technology sales professional with more than 20 years of industry experience.

Subscribe for new engineering and hardware deep dives.

────────────────────

CONNECT:

Website: SiliconToSoftware.com X: @SiToSoftware Instagram: @silicon_to_software YouTube: Silicon to Software

#SmartCity #AIHardware #EdgeComputing