## Episode Summary

In this episode, we cover:

- **Tiara: A Programmable Line-Rate ISA for Remote Memory Access** (arXiv)

- **HierSVA: A Data Synthesis Pipeline, Dataset, and Benchmark for LLM-Driven Hierarchical Hardware Formal Verification** (arXiv)

- **Using a Performance Model to Implement a Superscalar CVA6** (riscv_news)

- **Ben C.'s Clever Compiler Imports Verilog Designs, Including a Working RISC-V CPU, Into Factorio - Hackster.io** (google_riscv)

- **Now you can put a SpacemiT K3 RISC-V processor in a Framework Laptop 13 - Liliputing** (google_riscv)

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*Sponsored by LimitLess AI*