Condor Currents

## Episode Summary

In this episode, we cover:

- **Efficient VLA Inference via Retrieval-Based Speculation and Hardware Acceleration** (arXiv)

- **SBA: A Practical Memory Performance Denial-of-Service Attack** (arXiv)

- **RISC-V for AI Acceleration: Panel Debates Custom Cores, Inference Limits and Verification - News and Statistics - IndexBox** (google_riscv)

- **Qwenputer, a RISC-V CPU inside a model’s weights - Adafruit** (google_riscv)

- **FURSOY publishes open-source RISC-V core that boots Linux and hits 500 MHz in synthesis - news.lavx.hu** (google_riscv)

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*Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

## Episode Summary

In this episode, we cover:

- **SPEC CPU2026 Under the Microscope: Programs, Phases, and Samples** (arXiv)

- **LLMRunner: Closed Workload Model Performance Testing Framework for LLM Servings** (arXiv)

- **Embedding RISC-V CPU Directly into AI Weights: Qwen3.5-4B-Based "Qwenputer" Released - finance.biggo.com** (google_riscv)

- **DAMO Academy's XuanTie XL-300 Interconnect IP Links Up to Eight RISC-V Cores With 32MB of L3 - Pandaily** (google_riscv)

- **AI agent designs RISC-V processor in 12 hours from 219-word specification - Mezha** (google_riscv)

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*Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

## Episode Summary

In this episode, we cover:

- **SlipStream: Enabling HBF for GPU Systems by Mitigating the Latency and SRAM Overheads** (arXiv)

- **NVIDIA Vera: A Microarchitecture-Level Comparison with Grace, Turin, and Granite Rapids** (arXiv)

- **How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours - IEEE Spectrum** (google_riscv)

- **The Memory Challenge Of Physical AI** (semiengineering)

- **RISC-V SoCs Zero in on Physical AI Applications - Electronic Design** (google_riscv)

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*Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

## Episode Summary

In this episode, we cover:

- **WINIC: An Automatic Cycle-Accurate Multi-Platform Microbenchmarking Tool for Instruction Performance Metrics** (arXiv)

- **Efficient VLA Inference via Retrieval-Based Speculation and Hardware Acceleration** (arXiv)

- **As Alibaba launches server-grade RISC-V CPU, Beijing throws its weight behind ISA - The Register** (google_riscv)

- **How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours - IEEE** (google_riscv)

- **New RISC-V microprocessor can run CPU, GPU, and NPU workloads simultaneously - Tom's Hardware** (google_riscv)

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*Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

## Episode Summary

In this episode, we cover:

- **Uncovering the Memory Hierarchy of Modern NVIDIA GPUs for Accurate Simulation** (arXiv)

- **Augur: An Online Learning-based Hardware Data Prefetcher using Reservoir Computing** (arXiv)

- **For Automakers, RISC-V Isn’t Just About Ownership: It’s About Freedom of Choice** (riscv_news)

- **AMD Zen 6 Architecture Brings A Phenomenal 27% IPC Increase Over Zen 5: Full Architecture Breakdown – Up To 256 Cores, 12.8 GT/s MRDIMMs, A New ISA & More - Wccftech** (google_arch)

- **Bendable non-silicon RISC-V microprocessor - Nature** (google_riscv)

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*Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

## Episode Summary

In this episode, we cover:

- **RISC-V Revolution: How Open Processors Are Changing the CPU Market - Geeky Gadgets** (google_riscv)

- **SpacemiT to launch server-class RISC-V processor following capital injection - South China Morning Post** (google_riscv)

- **RISC-V CPU Performance Up 8x In Five Years: SiFive HiFive Unmatched To SpacemiT K3 - Phoronix** (google_riscv)

- **Kari Hepola: Custom tools make RISC-V processors faster and easier to design - www.tuni.fi** (google_riscv)

- **Alibaba unveils ‘highest performing RISC-V CPU in the world’ to power ‘Agentic AI’ - The Times of India** (google_riscv)

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*Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

## Episode Summary

In this episode, we cover:

- **RoadBlock: Rethinking GPU Tensor Core Microarchitecture for Emerging Microscaling Format Support** (arXiv)

- **BitDecoding-FP4: Native FP4 KV Cache Decoding via Algorithm-System Co-Design** (arXiv)

- **AI agent designs a complete RISC-V CPU from a 219-word spec sheet in just 12 hours — comparably simple design required 'many tens of billions of tokens' - Tom's Hardware** (google_riscv)

- **Security Researchers Find Current RISC-V CPU Implementations Coming Up Short - Phoronix** (google_riscv)

- **Openchip unveils BER10 RISC-V processor as Europe pursues greater digital sovereignty - New Electronics** (google_riscv)

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*Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

## Episode Summary

In this episode, we cover:

- **A Controlled Experimental Evaluation of Configuration and Cache Architecture in LLM Serving Engines** (arXiv)

- **CAMP: Context-Aware Mapping and Placement for LLMs on 3D-IMC Arrays** (arXiv)

- **Design of a low-power RISC-V based intelligent endoscopy detection processor: EndoRISC-V - Nature** (google_riscv)

- **SpacemiT Announces The V100 Server-Class RISC-V Processor - Phoronix** (google_riscv)

- **India targets creating homegrown GPUs within 2 years and plans to commercialize indigenous SHAKTI and VEGA RISC-V processors — sees AI boom as a potential repeat of the Y2K opportunity for its IT industry - Tom's Hardware** (google_riscv)

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*Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

## Episode Summary

In this episode, we cover:

- **NUMA-Torch: Compiler-Driven NUMA-Aware LLM Prefill on Multi-Socket CPUs** (arXiv)

- **Should You Split Decode? Disaggregation Across Future Models and Accelerators** (arXiv)

- **A RISC-V Based TEE With AMD Zen 6 CPUs - Phoronix** (google_riscv)

- **2026 Retrocomputing Challenge: Custom RISC-V Processor For Retro System - Hackaday** (google_riscv)

- **India Bets on Homegrown Chips: A Domestic GPU in 24 Months, RISC-V Processors Headed to Market in Parallel - BigGo Finance** (google_riscv)

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*Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

## Episode Summary

In this episode, we cover:

- **Renesas Unveils the First Generation of Own 32-bit RISC-V CPU Core Ahead of Competition - Renesas** (google_riscv)

- **Renesas Pioneers RISC-V Technology With RZ/Five General-Purpose MPUs Based on 64-Bit RISC-V CPU Core - Renesas** (google_riscv)

- **NextSilicon Productizes Arbel RISC-V Core Into 64-Core Enterprise Processor - Quantum Zeitgeist** (google_arch)

- **SoCMake: Modular RISC-V SoCs for Radiation-Harsh and Safety-Critical Environments** (riscv_news)

- **AI model gets a 32-bit RISC-V CPU compiled directly into its weights, then runs DOOM on it — experimental AI model can run Doom and C code using its own weights as RAM - Tom's Hardware** (google_riscv)

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*Sponsored by Ada, Ago Consulting, and Zen Semiconductor*