Condor Currents

Condor Currents

By Condor ComputingTechnologyTech News
Download on the App Store

Condor Currents episodes

  • Cache-Aware Conv3D Lowering Across Embedded World-Model Decoders
    ## Episode Summary
    In this episode, we cover:
    - **Cache-Aware Conv3D Lowering Across Embedded World-Model Decoders** (arXiv)
    - **DPS: Dual-Mode Precision LLM Serving with Semi-Unified Memory** (arXiv)
    - **Nuvacore’s WarpCore Ditches The ISA-First Playbook, Building CPU Silicon Before Deciding On x86, Arm, Or RISC-V - wccftech.com** (google_riscv)
    - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - Phoronix** (google_riscv)
    - **The Evolution of CPU Architectures – From Intel 4004 To Modern SoCs - wccftech.com** (google_arch)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    0 min
  • Bandwidth, Not FLOPS: FFT Kernels, Matrix Units and SAR Imaging on Apple M6
    ## Episode Summary
    In this episode, we cover:
    - **Bandwidth, Not FLOPS: FFT Kernels, Matrix Units and SAR Imaging on Apple M6** (arXiv)
    - **Improving Indirect Branch Prediction in Interpreters via Hardware/Software Co-Design** (arXiv)
    - **Checking In On The ISA Wars And Its Impact On CPU Architectures - hackaday.com** (google_arch)
    - **Nuvacore’s WarpCore Ditches The ISA-First Playbook, Building CPU Silicon Before Deciding On x86, Arm, Or RISC-V - Wccftech** (google_riscv)
    - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - Business Wire** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    0 min
  • QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System Stacks - IEEE Computer Society
    ## Episode Summary
    In this episode, we cover:
    - **QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System Stacks - IEEE Computer Society** (google_arch)
    - **China's LineShine tops supercomputer ranking with all-CPU architecture - China Daily** (google_arch)
    - **Zhihe A210 octa-core RISC-V SoC with 12 TOPS NPU powers SoM-based development board - CNX Software** (google_riscv)
    - **India unveils a homegrown dual-core 1GHz RISC-V processor, the DHRUV64 - The Register** (google_riscv)
    - **RISC-V Soft Cores Go 64-Bit With Efinix Sapphire RV64 - The Futurum Group** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    15 min
  • The KV Cache Is the New Memory Wall
    ## Episode Summary
    In this episode, we cover:
    - **The KV Cache Is the New Memory Wall** (arXiv)
    - **PipeDRAM: A Data-Transposition-Free In-DRAM Architecture with Hardware/Software Pipelining** (arXiv)
    - **Bit-Brick K1: Raspberry Pi 5 alternative with different CPU architecture, M.2 and PCIe support launches - Notebookcheck** (google_arch)
    - **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on Board - TechPowerUp** (google_arch)
    - **How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours - IEEE Spectrum** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    15 min
  • HeteroReason: Heterogeneous FPGA-GPU Acceleration for Disaggregated Speculative Reasoning
    ## Episode Summary
    In this episode, we cover:
    - **HeteroReason: Heterogeneous FPGA-GPU Acceleration for Disaggregated Speculative Reasoning** (arXiv)
    - **SARA: SLO-Aware Resource Allocation for Disaggregated Agentic LLM Services** (arXiv)
    - **For Automakers, RISC-V Isn’t Just About Ownership: It’s About Freedom of Choice** (riscv_news)
    - **Performance aware shared memory hierarchy model for multicore processors - Nature** (google_arch)
    - **AheadComputing Inc. Raises Additional $30M Seed2 Round to Reimagine CPU Architecture - HPCwire** (google_arch)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    18 min
  • Exploiting Decompression Latency for Covert Channels in Inter-Line-Compressed LLCs
    ## Episode Summary
    In this episode, we cover:
    - **Exploiting Decompression Latency for Covert Channels in Inter-Line-Compressed LLCs** (arXiv)
    - **Paging the Experts: A Reproducible Characterization of Flash-Backed MoE Inference on iPhone** (arXiv)
    - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_arch)
    - **The key CPU architecture you've never heard of: RISC-V - RedShark News** (google_arch)
    - **The RISC-V Vector Extensions for AI - Jon Peddie Research** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    16 min
  • Bridging LLM Serving and CXL-SSDs with Chunk-Aware KV Cache Management
    ## Episode Summary
    In this episode, we cover:
    - **Bridging LLM Serving and CXL-SSDs with Chunk-Aware KV Cache Management** (arXiv)
    - **HBF-Sim: An Extensible HBF Simulator for Large-scale GPU Memory Systems** (arXiv)
    - **RISC-V vs ARM: Which Instruction Set Architecture Will Dominate the Future? - Electropages** (google_arch)
    - **NextSilicon to Productize Arbel RISC-V Core into 64-Core Enterprise Processor for AI and HPC - HPCwire** (google_riscv)
    - **Security Researchers Find Current RISC-V CPU Implementations Coming Up Short - Phoronix** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    0 min
  • PrefixBench-H100: Characterizing Prefix Reuse and Time-to-First-Token in H100 LLM Serving
    ## Episode Summary
    In this episode, we cover:
    - **PrefixBench-H100: Characterizing Prefix Reuse and Time-to-First-Token in H100 LLM Serving** (arXiv)
    - **Understanding and Exploiting Diagonal Attention Sparsity in Autoregressive Image Generation** (arXiv)
    - **Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday** (google_arch)
    - **Kari Hepola: Custom tools make RISC-V processors faster and easier to design - tuni.fi** (google_riscv)
    - **Enabling Comprehensive CWE-based Assurance for RISC-V Processors - semiengineering.com** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    18 min
  • RISC-V and machine learning: a survey
    ## Episode Summary
    In this episode, we cover:
    - **RISC-V and machine learning: a survey** (arXiv)
    - **MeshKV: A Network-on-Chip KV Cache Fabric for Scalable Transformer Decoding Accelerators** (arXiv)
    - **QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System Stacks - computer.org** (google_arch)
    - **nRF54LC10A SoC features Cortex-M33, RISC-V coprocessor, Bluetooth LE, Thread and Zigbee - LinuxGizmos.com** (google_riscv)
    - **SpacemiT to launch server-class RISC-V processor following capital injection - South China Morning Post** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    16 min
  • Quantifying the Effect of HCLs on a Fixed-Microarchitecture MXFP4 Accelerator
    ## Episode Summary
    In this episode, we cover:
    - **Quantifying the Effect of HCLs on a Fixed-Microarchitecture MXFP4 Accelerator** (arXiv)
    - **HBFlex: A Flexible Memory System for Bridging Fine-Grained LLM States and Coarse-Grained HBF Parallel Execution** (arXiv)
    - **Design of a low-power RISC-V based intelligent endoscopy detection processor: EndoRISC-V - nature.com** (google_riscv)
    - **Enabling Comprehensive CWE-based Assurance for RISC-V Processors - Semiconductor Engineering** (google_riscv)
    - **Armaan Gomes and Friends Deliver Playable Doom on a Whole New Platform: A Custom RISC-V CPU - Hackster.io** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    17 min

About Condor Currents

From the publisher's feed

Condor Currents delivers concise breakdowns of the latest computer architecture research and RISC-V developments. Each episode covers recent arXiv papers on data prefetching, branch prediction, and…