Condor Currents

Condor Currents

By Condor ComputingTechnologyTech News
Download on the App Store

Condor Currents episodes

  • PAGE404: Breaking GPU Isolation Through Hardware-assisted Page Migration
    ## Episode Summary
    In this episode, we cover:
    - **PAGE404: Breaking GPU Isolation Through Hardware-assisted Page Migration** (arXiv)
    - **MemLLM: End-to-end In-Storage Acceleration of On-device Retrieval-Augmented Generation using Precomputed KV Caches** (arXiv)
    - **Linux 7.2-rc2 Raising The Default RISC-V 64-bit CPU Limit To 256 Cores - Phoronix** (google_riscv)
    - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - TechPowerUp** (google_riscv)
    - **SoCMake: Modular RISC-V SoCs for Radiation-Harsh and Safety-Critical Environments** (riscv_news)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    0 min
  • HBFSim: A Simulator for Exploring HBF in Memory Hierarchies for LLMs
    ## Episode Summary
    In this episode, we cover:
    - **HBFSim: A Simulator for Exploring HBF in Memory Hierarchies for LLMs** (arXiv)
    - **A Hybrid GPU and Processing-Near-Memory Architecture with Shared DRAM for Efficient Prefill-Decode Disaggregation** (arXiv)
    - **RISC-V extensions for high performance embedded computing ... - eeNews Europe** (google_riscv)
    - **Server-class 46-core RISC-V CPU runs mainstream Linux - LinuxGizmos.com** (google_riscv)
    - **SpacemiT V100 processor: 46-core RISC-V server - NeoTeo** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    14 min
  • Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday
    ## Episode Summary
    In this episode, we cover:
    - **Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday** (google_arch)
    - **RISC-V vs ARM: Which Instruction Set Architecture Will Dominate the Future? - Electropages** (google_arch)
    - **Nvidia Vera CPU Architecture: Max single-threaded CPU at scale for agents - GamesBeat** (google_arch)
    - **SpacemiT Announces The V100 Server-Class RISC-V Processor - Phoronix** (google_riscv)
    - **RISC-V Soft Cores Go 64-Bit With Efinix Sapphire RV64 - The Futurum Group** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    16 min
  • FORGE: Procedural Weight Generation for Sparse MoE Inference
    ## Episode Summary
    In this episode, we cover:
    - **FORGE: Procedural Weight Generation for Sparse MoE Inference** (arXiv)
    - **AlignPred: Error-Controlled KV Cache Compression via Alignment and Predictive Coding** (arXiv)
    - **Deja Vu: A Brief History of Every Mac CPU Architecture - How-To Geek** (google_arch)
    - **Design Conductor: An agent autonomously builds a 1.5 GHz Linux-capable RISC-V CPU - alphaXiv** (google_riscv)
    - **Efinix Announces New Sapphire RV64 SoC, Bringing 64-Bit RISC-V Performance to Embedded FPGA Designs - Embedded Computing Design** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    18 min
  • Foundations of Hardware-Software Leakage Contracts
    ## Episode Summary
    In this episode, we cover:
    - **Foundations of Hardware-Software Leakage Contracts** (arXiv)
    - **PAGE404: Breaking GPU Isolation Through Hardware-assisted Page Migration** (arXiv)
    - **The Evolution of CPU Architectures – From Intel 4004 To Modern SoCs - Wccftech** (google_arch)
    - **QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System Stacks - IEEE Computer Society** (google_arch)
    - **RISC-V Soft Processor System on DE10-Lite - Hackster.io** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    18 min
  • Top-Down Microarchitecture Analysis Without Causal Modelling Is Dangerous!
    ## Episode Summary
    In this episode, we cover:
    - **Top-Down Microarchitecture Analysis Without Causal Modelling Is Dangerous!** (arXiv)
    - **Minimum RISC-V: Maximum FPGA Efficiency** (arXiv)
    - **The key CPU architecture you've never heard of: RISC-V - Red Shark News** (google_arch)
    - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - Phoronix** (google_riscv)
    - **Performance aware shared memory hierarchy model for multicore processors - Nature** (google_arch)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    17 min
  • TALU: A Reconfigurable Tiled-ALU Grid for RISC-V
    ## Episode Summary
    In this episode, we cover:
    - **TALU: A Reconfigurable Tiled-ALU Grid for RISC-V** (arXiv)
    - **CacheSmith: Accurate RAG Serving under Latency SLOs with Adaptive KV Reuse** (arXiv)
    - **Nuvacore’s WarpCore Ditches The ISA-First Playbook, Building CPU Silicon Before Deciding On x86, Arm, Or RISC-V - Wccftech** (google_riscv)
    - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - Business Wire** (google_riscv)
    - **Meta’s Muse AI Agent Just Designed A Crypto-Specific SoC On The RISC-V Architecture For $2,000 To Transform The Thru Blockchain Into “The Fastest On Earth” - Wccftech** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    16 min
  • Programmable Data Layouts via On-The-Fly Data Transformation
    ## Episode Summary
    In this episode, we cover:
    - **Programmable Data Layouts via On-The-Fly Data Transformation** (arXiv)
    - **Simulate Before You Scale: High-Fidelity LLM Inference Planning Without GPUs** (arXiv)
    - **China's LineShine tops supercomputer ranking with all-CPU architecture - China Daily** (google_arch)
    - **Zhihe A210 octa-core RISC-V SoC with 12 TOPS NPU powers SoM-based development board - CNX Software** (google_riscv)
    - **Security Researchers Find Current RISC-V CPU Implementations Coming Up Short - Phoronix** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    21 min
  • Read What Matters: Query-Adaptive Quantization for KV Caches
    ## Episode Summary
    In this episode, we cover:
    - **Read What Matters: Query-Adaptive Quantization for KV Caches** (arXiv)
    - **A Pipelined FPGA Architecture for Banded Sparse Matrix Dense Matrix Multiplication in Longformer** (arXiv)
    - **Bit-Brick K1: Raspberry Pi 5 alternative with different CPU architecture, M.2 and PCIe support launches - Notebookcheck** (google_arch)
    - **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on Board - TechPowerUp** (google_arch)
    - **How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours - IEEE Spectrum** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    17 min
  • CacheFlex: Direct Software-Managed Access to Higher-Level Cache for Scalable Vector Support
    ## Episode Summary
    In this episode, we cover:
    - **CacheFlex: Direct Software-Managed Access to Higher-Level Cache for Scalable Vector Support** (arXiv)
    - **Taking Tokenization off the Host for Agentic LLM Serving** (arXiv)
    - **For Automakers, RISC-V Isn’t Just About Ownership: It’s About Freedom of Choice** (riscv_news)
    - **What Is a Microarchitecture? Understanding Processors and Register Files in an ARM Core - All About Circuits** (google_arch)
    - **Armaan Gomes and Friends Deliver Playable Doom on a Whole New Platform: A Custom RISC-V CPU - Hackster.io** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    0 min

About Condor Currents

From the publisher's feed

Condor Currents delivers concise breakdowns of the latest computer architecture research and RISC-V developments. Each episode covers recent arXiv papers on data prefetching, branch prediction, and…