Condor Currents

Condor Currents

By Condor ComputingTechnologyTech News
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Condor Currents episodes

  • A Framework for Accelerating Transformer Inference on RISC-V for Edge AI
    ## Episode Summary
    In this episode, we cover:
    - **A Framework for Accelerating Transformer Inference on RISC-V for Edge AI** (arXiv)
    - **ECO: Energy-Oriented Configuration Optimization for Attention FFN Disaggregated LLM Serving** (arXiv)
    - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_arch)
    - **The key CPU architecture you've never heard of: RISC-V - RedShark News** (google_arch)
    - **Efinix Goes 64-Bit with Its Latest Sapphire SoC FPGA Cores, Based on the RISC-V Architecture - Hackster.io** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    15 min
  • SUSpMV: A High Frequency Sparse Matrix Vector Multiplier on HBM Enabled FPGA written in SUS
    ## Episode Summary
    In this episode, we cover:
    - **SUSpMV: A High Frequency Sparse Matrix Vector Multiplier on HBM Enabled FPGA written in SUS** (arXiv)
    - **BenchmarkAnything: Agent-Driven Construction of Simulator-Ready Microarchitecture Benchmarks** (arXiv)
    - **Nuvia Architects’ New CPU Core Can Use Arm, RISC-V or x86 - HWCooling.net** (google_riscv)
    - **Upbeat Technology’s Bluemag Pi Pairs RISC-V Processors and AI Inference for Advanced Flight Control - Embedded Computing Design** (google_riscv)
    - **Efinix® Brings 64-Bit RISC-V Performance to Embedded FPGA Designs With New Sapphire™ RV64 SoC - Yahoo Finance** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    18 min
  • CacheFit: The Rising Cost of Cache Replacement and Constraint-Driven Redesign of Last-Level Cache Replacement Policies
    ## Episode Summary
    In this episode, we cover:
    - **CacheFit: The Rising Cost of Cache Replacement and Constraint-Driven Redesign of Last-Level Cache Replacement Policies** (arXiv)
    - **CXDVirt: Low Latency Kernel Module Based CXL-SSD Emulation** (arXiv)
    - **Nuvia’s Architects Now Preparing a CPU for Arm, RISC-V or x86 - HWCooling.net** (google_riscv)
    - **Openchip unveils BER10 RISC-V processor as Europe pursues greater digital sovereignty - New Electronics** (google_riscv)
    - **Enabling Comprehensive CWE-based Assurance for RISC-V Processors - Semiconductor Engineering** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    0 min
  • CHiRP: Control-Flow History Reuse Prediction
    ## Episode Summary
    In this episode, we cover:
    - **CHiRP: Control-Flow History Reuse Prediction** (arXiv)
    - **SVRF: Efficient Register Storage for Long-Vector Architectures** (arXiv)
    - **WheatForce: Learning From CPU Architecture Mistakes - Hackaday** (google_arch)
    - **Efinix Sapphire RV64 SoC – Configurable RISC-V soft-cores with DDR3, LPDDR4x, and HyperRAM for Efinix FPGAs - CNX Software** (google_riscv)
    - **RISC-V Processor Advances Local Chip Design - Open Source For You** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    0 min
  • Trail: Scalable and Low-Cost Temporal TLB Prefetching via Page-Table-Embedded Deltas
    ## Episode Summary
    In this episode, we cover:
    - **Trail: Scalable and Low-Cost Temporal TLB Prefetching via Page-Table-Embedded Deltas** (arXiv)
    - **CACHEFORGE: LLM-Guided End-to-End Generative Cache Replacement Policy for Performance and Hardware Efficiency** (arXiv)
    - **Efinix Adds 64-Bit RISC-V SoC with Linux and DDR Support - www.embedded.com** (google_riscv)
    - **RISC-V CPU Performance Up 8x In Five Years: SiFive HiFive Unmatched To SpacemiT K3 - Phoronix** (google_riscv)
    - **Prompt to tape out: Autonomous AI agent builds 1.5 GHz RISC-V CPU - Adafruit** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    17 min
  • Characterizing High Bandwidth Flash for LLM Serving
    ## Episode Summary
    In this episode, we cover:
    - **Characterizing High Bandwidth Flash for LLM Serving** (arXiv)
    - **Request Order Matters: Cache-History Sensitivity in Selective KV-Cache Reuse for Rolling Agents** (arXiv)
    - **Design of a low-power RISC-V based intelligent endoscopy detection processor: EndoRISC-V - Nature** (google_riscv)
    - **Your Nvidia GPU has dozens of RISC-V cores inside it, and one of them took over a huge part of the graphics driver - XDA** (google_riscv)
    - **Efinix Announces New Sapphire RV64 SoC, Bringing 64-Bit RISC-V Performance to Embedded FPGA Designs - embeddedcomputing.com** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    16 min
  • ServeTwin: A Benchmark-Validated Simulator for Distributed LLM Architecture Exploration
    ## Episode Summary
    In this episode, we cover:
    - **ServeTwin: A Benchmark-Validated Simulator for Distributed LLM Architecture Exploration** (arXiv)
    - **AdaptViT: Runtime-Adaptive Vision Transformer Deployment on Custom RISC-V** (arXiv)
    - **RISC-V extensions for high performance embedded computing ... - eeNews Europe** (google_riscv)
    - **Efinix Adds 64-Bit RISC-V SoC for FPGA-Based Embedded Systems - EE Times Asia** (google_riscv)
    - **Efinix Adds 64-Bit RISC-V SoC with Linux and DDR Support - embedded.com** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    0 min
  • Where Activation Sparsity and KV-Cache Sparsity Cross in LLM Decoding
    ## Episode Summary
    In this episode, we cover:
    - **Where Activation Sparsity and KV-Cache Sparsity Cross in LLM Decoding** (arXiv)
    - **U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC** (arXiv)
    - **Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday** (google_arch)
    - **How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours - spectrum.ieee.org** (google_riscv)
    - **Zhihe A210 octa-core RISC-V SoC with 12 TOPS NPU powers SoM-based development board - cnx-software.com** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    21 min
  • Efficient Linkage-Based Compartmentalization on CHERI
    ## Episode Summary
    In this episode, we cover:
    - **Efficient Linkage-Based Compartmentalization on CHERI** (arXiv)
    - **SPIMOE: Exploiting Hybrid Sparsity for Reasoning MoE Inference on Heterogeneous PIM Architectures** (arXiv)
    - **HBF for High-Throughput LLM Serving (UC Berkeley, FuriosaAI)** (semiengineering)
    - **Efinix Adds 64-Bit RISC-V SoC with Linux and DDR Support - embedded.com** (google_riscv)
    - **Efinix Announces New Sapphire RV64 SoC, Bringing 64-Bit RISC-V Performance to Embedded FPGA Designs - Embedded Computing Design** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    16 min
  • Characterizing High Bandwidth Flash for LLM Serving
    ## Episode Summary
    In this episode, we cover:
    - **Characterizing High Bandwidth Flash for LLM Serving** (arXiv)
    - **STELLA: A 16nm Spatio-Temporal Elastic Low-Latency CGRA for Multi-Stage Pipelined Applications** (arXiv)
    - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - phoronix.com** (google_riscv)
    - **The Evolution of CPU Architectures – From Intel 4004 To Modern SoCs - Wccftech** (google_arch)
    - **Nvidia Vera CPU Architecture: Max single-threaded CPU at scale for agents - GamesBeat** (google_arch)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    0 min

About Condor Currents

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Condor Currents delivers concise breakdowns of the latest computer architecture research and RISC-V developments. Each episode covers recent arXiv papers on data prefetching, branch prediction, and…