Condor Currents

Condor Currents

By Condor ComputingTechnologyTech News
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Condor Currents episodes

  • In-depth data movement characterization of DNA read mapping algorithms
    ## Episode Summary
    In this episode, we cover:
    - **In-depth data movement characterization of DNA read mapping algorithms** (arXiv)
    - **SparseForge: Beyond Spike Sparsity toward Hardware-Exploitable Neuron Pruning for Efficient SNN Acceleration** (arXiv)
    - **The key CPU architecture you've never heard of: RISC-V - Red Shark News** (google_riscv)
    - **Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday** (google_arch)
    - **Server-class 46-core RISC-V CPU runs mainstream Linux - LinuxGizmos.com** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    17 min
  • Randomized Caches in Hardware: Challenges and Trade-offs
    ## Episode Summary
    In this episode, we cover:
    - **Randomized Caches in Hardware: Challenges and Trade-offs** (arXiv)
    - **HyPAIC: Personal AI Computer with High Bandwidth Flash for High Performance Trillion-Parameter LLM Inference** (arXiv)
    - **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on Board - TechPowerUp** (google_arch)
    - **India unveils a homegrown dual-core 1GHz RISC-V processor, the DHRUV64 - The Register** (google_riscv)
    - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - Business Wire** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    0 min
  • MCF: A Memory- and Communication-Aware Co-Designed Framework for Long-Context LLM Inference
    ## Episode Summary
    In this episode, we cover:
    - **MCF: A Memory- and Communication-Aware Co-Designed Framework for Long-Context LLM Inference** (arXiv)
    - **Automated Multi-Line Bug Repair Using Model Checker Aided LLMs: A Case Study on RISC-V Processors** (arXiv)
    - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_arch)
    - **China's LineShine tops supercomputer ranking with all-CPU architecture - China Daily** (google_arch)
    - **Bit-Brick K1: Raspberry Pi 5 alternative with different CPU architecture, M.2 and PCIe support launches - Notebookcheck** (google_arch)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    17 min
  • DeepInfer-Mac: Running a 750B-Class MoE on a 24 GB Laptop
    ## Episode Summary
    In this episode, we cover:
    - **DeepInfer-Mac: Running a 750B-Class MoE on a 24 GB Laptop** (arXiv)
    - **SPARTA: A Sparse Ternary LLM Accelerator with Adaptive Attention and Unified Datapath for Long-Context Edge Inference** (arXiv)
    - **As Alibaba launches server-grade RISC-V CPU, Beijing throws its weight behind ISA - The Register** (google_riscv)
    - **How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours - IEEE Spectrum** (google_riscv)
    - **New RISC-V microprocessor can run CPU, GPU, and NPU workloads simultaneously - Tom's Hardware** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    17 min
  • Toward Open ISA Supercomputing: A Comparative Study of RISC-V, Arm, and x86 Architectures on HPC Workloads
    ## Episode Summary
    In this episode, we cover:
    - **Toward Open ISA Supercomputing: A Comparative Study of RISC-V, Arm, and x86 Architectures on HPC Workloads** (arXiv)
    - **PaFeDSE: Pareto-Feedback-Guided Microarchitecture Design Space Exploration for Efficient Pareto Search** (arXiv)
    - **Ultra-Low-Latency IPC: RISCVLinux Part 3 - Hackster.io** (google_riscv)
    - **For Automakers, RISC-V Isn’t Just About Ownership: It’s About Freedom of Choice** (riscv_news)
    - **SiFive makes the case for RISC-V as the control layer for custom AI accelerators - Jon Peddie** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    17 min
  • Toward Open ISA Supercomputing: A Comparative Study of RISC-V, Arm, and x86 Architectures on HPC Workloads
    ## Episode Summary
    In this episode, we cover:
    - **Toward Open ISA Supercomputing: A Comparative Study of RISC-V, Arm, and x86 Architectures on HPC Workloads** (arXiv)
    - **HAWK: Heterogeneity-Aware KV Cache Transfer for Efficient GPU-NPU Phase-Disaggregated LLM Inference** (arXiv)
    - **Efinix Sapphire RV64 SoC – Configurable RISC-V soft-cores with DDR3, LPDDR4x, and HyperRAM for Efinix FPGAs - CNX Software** (google_riscv)
    - **Efinix Goes 64-Bit with Its Latest Sapphire SoC FPGA Cores, Based on the RISC-V Architecture - Hackster.io** (google_riscv)
    - **RISC-V CPU Performance Up 8x In Five Years: SiFive HiFive Unmatched To SpacemiT K3 - Phoronix** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    14 min
  • panvram: GPU-resident random access to a human pangenome cohort
    ## Episode Summary
    In this episode, we cover:
    - **panvram: GPU-resident random access to a human pangenome cohort** (arXiv)
    - **BS-Spec: BFP-Based Bit-Sharing for Self-Speculative LLM Decoding with LUT-Driven Mixed-Precision Acceleration** (arXiv)
    - **Nuvia Architects’ New CPU Core Can Use Arm, RISC-V or x86 - HWCooling.net** (google_riscv)
    - **Lanxin Computing Unveils RISC-V Supernode Built on Its 48-Core LX500 Inference Chip - Pandaily** (google_riscv)
    - **Upbeat Technology’s Bluemag Pi Pairs RISC-V Processors and AI Inference for Advanced Flight Control - Embedded Computing Design** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    22 min
  • Proba: A High-Performance, Low-Traffic Probabilistic Spatial Memory Streaming Prefetcher
    ## Episode Summary
    In this episode, we cover:
    - **Proba: A High-Performance, Low-Traffic Probabilistic Spatial Memory Streaming Prefetcher** (arXiv)
    - **Stop Paying by the Letter: Accelerating Full-Chip RTL Simulation with Host-Side Tokenized Logging** (arXiv)
    - **UltraRISC Shows UR-CP400 RISC-V Core IP: RVA23, 8-Wide Out-of-Order, Delivery in Q1 2027 - Pandaily** (google_riscv)
    - **SpacemiT Pairs V100 RISC-V Server CPU With Three Servers, Kunlunxin M100 Validation and Linux - Pandaily** (google_riscv)
    - **RISC-V data center processors: server requirements - NeoTeo** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    17 min
  • SnakeCharmer: Orchestrating Utility, Timeliness, and Placement in GPU Prefetching
    ## Episode Summary
    In this episode, we cover:
    - **SnakeCharmer: Orchestrating Utility, Timeliness, and Placement in GPU Prefetching** (arXiv)
    - **Reorienting the Vector Axis: Restructuring FlashAttention for Long-Vector Processors** (arXiv)
    - **Chinese chipmakers roll out new RISC-V server CPUs for AI demand - Global Times** (google_riscv)
    - **DAMO Academy's XuanTie E908A Is an Automotive RISC-V CPU IP Aimed at ASIL-B and ASIL-D Designs - Pandaily** (google_riscv)
    - **Design of a low-power RISC-V based intelligent endoscopy detection processor: EndoRISC-V - Nature** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    17 min
  • HAWK: Heterogeneity-Aware KV Cache Transfer for Efficient GPU-NPU Phase-Disaggregated LLM Inference
    ## Episode Summary
    In this episode, we cover:
    - **HAWK: Heterogeneity-Aware KV Cache Transfer for Efficient GPU-NPU Phase-Disaggregated LLM Inference** (arXiv)
    - **Accelerating CPU Speculative Decoding via Unified Graph Execution and Transactional KV Isolation** (arXiv)
    - **Why Chip Design AI Benchmarks Must Go Beyond Functional Correctness** (eetimes)
    - **SpacemiT V100: New RISC-V Server Processor Combines 46 Cores, DDR5 and PCIe 5.0 - igor´sLAB** (google_riscv)
    - **Alibaba unveils automotive RISC-V processor IP and roadmap for self-driving and robotics - TechNode** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    17 min

About Condor Currents

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Condor Currents delivers concise breakdowns of the latest computer architecture research and RISC-V developments. Each episode covers recent arXiv papers on data prefetching, branch prediction, and…