What can AI actually do in 3D IC design today — and what's still science fiction?

What you’ll learn…

(01:25) Sudarshan's role leading global 3D IC software R&D at Siemens

(02:30) The real starting challenges of 3D IC design — and why there's no playbook yet

(05:25) Breaking down organizational silos between silicon, packaging, and mechanical teams

(05:49) Why semiconductor AI must be domain-specific, not just a chatbot

(10:34) AI as an engineering co-pilot for design space exploration

(13:38) Beyond design: AI's impact on materials, yield, and reliability prediction

(17:41) The shift toward AI-native, multiphysics co-optimization workflows

(21:16) Ethical pitfalls: explainability, data governance, and IP protection

(24:50) AI's role in the global, geopolitical semiconductor landscape

(27:48) How Siemens is building this with HEEDS and the Fuse EDA AI system

More about this episode…

In this episode of the Siemens 3D IC Podcast, host Tova Levy speaks with Sudarshan Deo, Software Engineering Manager for 3D IC at Siemens, about what AI can — and can't — actually do in 3D IC design today, and why the hype rarely matches the reality on the ground.

Sudarshan breaks down the biggest misconception in the field: that AI is either a magic box that will design chips end-to-end, or just hype dressed up as a buzzword. The truth, he argues, sits in between — semiconductor AI has to be domain-specific, physics-aware, and explainable, not a general-purpose chatbot. He walks through where AI is already delivering value, from narrowing design space exploration in chiplet partitioning and floor planning, to identifying promising materials and process combinations, to flagging reliability risks like thermal cycling and stress before they become expensive late-stage fixes.

The conversation also covers the organizational side — how 3D IC forces silicon, packaging, and mechanical teams out of their silos — and the ethical considerations that come with deeper AI adoption: explainability, data governance, and IP protection across foundries. Sudarshan closes by outlining Siemens' own approach, using Simcenter HEEDS for design space exploration and the Fuse EDA AI system to orchestrate engineering workflows end to end, while making clear that none of this replaces human judgment — it just changes how fast and how far that judgment can reach.

Ideal for: 3D IC and chiplet design engineers, EDA tool users, AI/ML practitioners in semiconductor workflows, packaging and reliability engineers, and anyone evaluating where AI genuinely helps versus where it's overhyped in chip design.

Connect with Tova Levy

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Connect with Sudarshan Deo

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Siemens EDA

What happens when a single untracked design change turns into a multi-billion-dollar public scandal?

What you’ll learn...

(00:00) Why data — not just design — is the hidden challenge behind every 3D IC

(01:55) A real-world case study: how poor traceability triggered a costly public recall

(04:06) The "mini database" problem: how tool sprawl scatters chip design data

(06:10) Why 3D IC makes data management so much harder than traditional SoC design

(08:32) What is an "atomic change," and why it's critical for design consistency

(10:15) Three foundational building blocks for managing data at scale

(12:42) IPLM vs. PLM: what's the difference, and why do you need both?

(15:19) The human cost of poor data management: hunting, silos, and burnout

(18:15) Why better data management makes onboarding faster and easier

(19:42) Inside the Perforce–Siemens partnership and what's next for 3D IC workflows

More about this episode…

In this episode of the Siemens 3D IC Podcast, host Tova Levy speaks with Vishal Moondhra, VP of Solutions at Perforce Software, about why data — not just design complexity — may be the biggest hidden risk in 3D IC development, and what teams can do about it.

Vishal opens with a real-world cautionary tale: a major chip company that shipped a security flaw across its product line, then discovered it lacked the traceability to know which variants needed the fix — a gap that led to a multi-billion-dollar hit to its market cap. From there, the conversation digs into why 3D IC makes this problem so much worse: every tool builds its own "mini database," changes ripple across interdependent dies and interposers, and AI-driven workflows are only multiplying the volume of data being generated. Vishal introduces the concept of the "atomic change" — capturing everything or nothing, so partial updates never slip through — and lays out the foundational building blocks of scalable data management, before drawing a clear line between PLM (product-level, slow-moving, heavily governed) and IPLM (design-level, fast-paced, daily). He closes by walking through the growing partnership between Perforce and Siemens, and how IPLM is being integrated across tools like Solido, Calibre, and Questa to give engineering teams a single source of truth.

Ideal for: 3D IC and SoC design teams, data and IP management leads, verification and design engineers, EDA tool users, and anyone responsible for traceability, compliance, or onboarding across a fast-scaling chip design organization.

Connect with Tova Levy

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Connect with Vishal Moondhra

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Perforce IPLM

What does it take to build a chip when the chip itself is an ecosystem — and the wire connecting everything has become the biggest bottleneck in modern semiconductors?

What you’ll learn...

(00:56) Bob's background and the founding of NHanced Semiconductors

(01:17) What "foundry agnostic" really means — and why trust matters

(03:16) How advanced packaging became a front-and-center design discipline

(04:30) Why wire — not transistors — now dominates power and delay

(06:46) The ecosystem village: EDA vendors, foundries, and test houses

(09:05) NHanced's collaboration with Siemens and Calibre 3D

(11:09) Making 3D IC accessible: MPWs, chiplets, and lower barriers to entry

(15:00) DFM advice: test planning, wire length, and stakeholder alignment

(18:30) Three to five years out: chiplets, photonics, and targeted designs

(23:05) Bob's message to the ecosystem: invest in the ADK/PDK flow

More about this episode...

In this episode of the Siemens 3D IC Podcast, host Tova Levy speaks with Bob Patti, President and CEO of NHanced Semiconductors, about what it takes to build and scale advanced packaging — and why the wire, not the transistor, has become the defining challenge of modern chip design.

Bob opens by explaining what makes NHhanced's foundry-agnostic model work: the company operates like a CMOS fab but builds no transistors, positioning it as a trusted neutral partner rather than a competitor to the foundries it works with. That neutrality is what allows NHanced to take material from virtually every major fab in the world and integrate it into complex 2.5D and 3D packages.

He then makes the case for why advanced packaging has moved from a backend afterthought to a front-and-center discipline. As transistors have scaled, wiring has gotten worse — now accounting for roughly 95% of the power and delay in modern circuitry. Advanced packaging attacks that problem directly, reducing wire length by orders of magnitude and enabling power reductions of up to 1000x in die-to-die interconnects. Achieving this requires the full ecosystem: EDA vendors, foundries, OSATs, and test houses collaborating from day one — with Siemens and Calibre 3D called out specifically for leading ADK development and making advanced packaging accessible to designers who aren't packaging specialists.

The episode closes with a look ahead: in the next three to five years, Bob sees a broader chiplet market, more off-the-shelf high-performance components including GaN and photonics, and a return to targeted, application-specific design — only now powered by heterogeneous integration.

Ideal for: 3D IC architects, advanced packaging engineers, chiplet ecosystem participants, EDA users, semiconductor startup founders, and anyone navigating the transition from monolithic SoC design to heterogeneous integration.

Connect with Tova Levy

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Connect with Bob Patti

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 NHanced Semiconductors Website

What does it take for one of the world's most complex engineering organisations to commit — fully — to 3D IC as a strategic direction? And what does that commitment reveal about the gaps the entire industry still needs to close?

What you’ll learn...

(02:07) Sujit's background: 30+ years in semiconductor processing and packaging, 300+ patents across X-ray lithography, CMP, and advanced thin film

(02:07) The three vectors driving Intel's 3D IC strategy: reticle size limits, AI/HPC memory bandwidth demands, and chiplet cost efficiency

(04:33) EMIB for 2.5D lateral die-to-die interconnects, and Foveros / Foveros Direct for 3D vertical copper-to-copper hybrid bonding

(06:48) Tackling design partitioning, thermal management, power delivery, and testability through STCO — System Technology Co-Optimization

(09:45) The biggest ecosystem challenge: breaking down cultural silos between silicon, package, and board design teams

(13:10) Why showing engineers real co-design data was the decisive factor in driving the mindset shift

(14:33) The EDA gaps still needing breakthroughs: full-stack digital twin, integrated multi-physics simulation, and cloud-based collaboration

(17:50) Killer app segments: AI and HPC, autonomous driving, communications bandwidth, and AI-driven EDA automation

(20:16) What the 3D IC era demands of engineers: T-shaped skills, cross-domain awareness, and real-world trade-off thinking

(24:57) Sujit's call to action: shift from tool-centric to system-level thinking, build the digital twin, standardise data exchange

More about this episode...

In this episode of the Siemens 3D IC Podcast, host Tova Levy speaks with Sujit Sharan, Intel Fellow in the Advanced Packaging Technology & Manufacturing Organization at Intel Corporation. With over 30 years in semiconductor processing and packaging and more than 300 issued patents, Sujit is one of the industry's foremost voices on making 3D IC real at production scale.

Three forces drive Intel's 3D IC strategy: reticle size limits on monolithic die; AI and HPC bandwidth demands requiring memory physically close to compute; and the cost efficiency of chiplet disaggregation. Intel's response is EMIB (Embedded Multi-die Interconnect Bridge) for lateral 2.5D die-to-die and die-to-HBM connections, and Foveros / Foveros Direct for vertical 3D stacking via copper-to-copper hybrid bonding — complementary technologies, not competing ones.

Managing this complexity means abandoning the silo model. Sujit's answer is STCO — System Technology Co-Optimization — treating silicon, package, and board as one integrated system. Cultural resistance was real; the solution was data, showing engineers the measurable gains co-design actually delivers.

The ultimate EDA goal is a full-stack digital twin spanning electrical, thermal, and thermomechanical analysis with near-real-time feedback. Siemens' Innovator 3D IC is a step in that direction, but standardised data exchange and cloud-based collaboration remain critical gaps. Sujit's call to action: EDA partners must shift from tool-centric to system-level thinking — and the whole industry needs to move together.

Ideal for: 3D IC architects, silicon IP designers, advanced packaging engineers, chiplet ecosystem participants, EDA users, and anyone navigating the shift from monolithic SoC design to heterogeneous, disaggregated integration.

Connect with Tova Levy

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Website

Connect with Sujit Sharan

LinkedIn

What happens when reliability can no longer be guaranteed by simply following the rules?

What you’ll learn...

(01:08) Andras's path from Flomerics and MicReD to Siemens EDA

(01:52) Why 3D IC reliability breaks from traditional 2D design

(05:04) The physics of CTE mismatch: warpage, cracking, delamination

(08:55) How performance-driven choices create a thermal time bomb

(11:31) Why failures happen at interfaces: solder, hybrid bonding, TIMs

(17:51) The human side: breaking silos between thermal, electrical, mechanical teams

(21:53) Siemens' digital continuity vision via Innovator3D IC Integrator

(22:11) The path to automation: agentic AI, natural-language tools

(26:43) Andras's key message: don't treat reliability as an afterthought

More about this episode…

In this episode of the Siemens 3D IC Podcast, host Tova Levy speaks with Andras Vass-Varnai, Solution Architect for 3D IC reliability at Siemens EDA, about why reliability can no longer be guaranteed simply by following design rules — and what it takes to build it in from day one.

Andras explains why 3D IC breaks the old reliability playbook: in 2D packaging, reliability is largely baked into process rules, but the sheer number of design choices in 3D IC — stacking, floor planning, materials, cooling — means reliability has to be checked continuously, not verified at the end. He walks through the physics behind this: CTE mismatch between stacked materials causes warpage that accumulates with thermal cycling, ultimately leading to cracking or delamination — and breaks down where failures actually happen, with solder interconnects as the likely weak link, hybrid bonding as a manufacturing-sensitive but operationally strong alternative, and thermal interface materials as a make-or-break factor.

The conversation also covers the organizational side — how breakdowns in communication between thermal, electrical, and mechanical teams become reliability risks of their own — and Siemens' approach to closing that gap through digital continuity, using Innovator3D IC Integrator to connect design disciplines, with a look ahead to how agentic AI could eventually automate the process. Andras closes with a clear message: break down the silos, and treat reliability as continuous from the start — not a final checkbox.

Ideal for: 3D IC and package architects, thermal and reliability engineers, signal/power integrity engineers, EDA tool users, and anyone working across the electrical-thermal-mechanical boundary in advanced packaging.

Connect with Tova Levy

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Website

Connect with Andras Vass-Varnai

LinkedIn

Siemens EDA

How do you secure a chip when the chip itself is made up of dies from multiple vendors and you can’t automatically trust any of them?

What you’ll learn...

(02:00) Chris’s background: 30 years of all-round experience

(03:00) What is hardware security? 

(05:30) Why hardware security is critical now & examples of security breaches

(08:30) Current security practices and required changes

(08:27) How security has traditionally been done — and what has to change

(11:13) The shift to a system-level view of security, especially in chiplet-based design

(11:00) Security challenges in 3D IC architectures 

(12:30) How can companies maintain IP integrity and prevent tampering throughout the 3D IC lifecycle?

(15:30) Maintaining IP integrity in 3D IC supply chains

(17:40) The Crypto Quantique / Siemens joint solution

(20:11) The most important thing designers and system architects should understand about hardware security.

More about this episode...

In this episode of the Siemens 3D IC Podcast, host Tova Levy speaks with Chris Jones, Director of Applications at Crypto Quantique, about what it takes to build hardware security into silicon from the ground up — and why the move to 3D IC architectures makes that challenge dramatically harder.

Chris opens by explaining what hardware security actually means at the silicon level: not just encryption, but a fixed, immutable boot sequence that runs from ROM every time a device powers on, verifying that firmware is signed and untampered before any application code is allowed to execute. It's a foundation that must be designed in not bolted on after the fact.

When chiplets from multiple vendors are stacked in a single package, every die-to-die interface becomes a potential attack surface. Chris explains why the industry must adopt a zero trust model — no chiplet should be assumed trustworthy simply because it's in the stack — and how physically unclonable functions (PUFs) enable each die to cryptographically prove its identity without ever exposing a secret key.

Chris and Tova also explore the industry forces pushing security up the agenda: the Trusted Computing Group and GlobalPlatform standardizing hardware roots of trust; NIST maintaining verified cryptographic standards; and the EU Cyber Resilience Act, requiring built-in security, OTA updates, and documented risk analysis for all connected products by December 2027.

The episode closes with the joint solution Crypto Quantique has developed with Siemens: QRoot Lite, a lightweight root-of-trust IP block now integrated into Siemens' Tessent EDA toolchain, automatically securing IJTAG-based DFT interfaces during manufacturing and ensuring test sequences can only be run by authorized parties.

For anyone working in 3D IC design, chiplet architecture, semiconductor security, or EDA, this episode offers a grounded, practical view of what it means to take hardware security seriously — from the first blank sheet of paper all the way through manufacturing.

Ideal for: 3D IC architects, SoC and ASIC designers, semiconductor security engineers, EDA tool users, IP vendors, system integrators, and anyone navigating the hardware security requirements of connected devices and 3D IC supply chains.

Connect with Tova Levy

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Website

Connect with Chris Jones

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Website

What does it actually mean for connectivity IP to stop being a supporting function — and become the layer that determines whether a 3D IC delivers on its promise?

What you’ll learn...

(02:45) Archana's background: semiconductor IP, high-speed clocking, and AI memory subsystems

(03:49) Alphawave Semi's role in 3D IC — and why the interconnect layer is now foundational

(05:40) 3D IC integration headaches: signal integrity, power delivery, and thermal hotspots

(07:59) IP development for 3D ICs: co-optimizing with packaging, interposers, and photonics

(10:02) Friction points: methodology inertia, ecosystem immaturity, and standardization vs. customization

(12:26) Balancing performance, reliability, and manufacturability — and Alphawave Semi's validation approach

(14:51) The magic wand pick: open chiplet interoperability and solving thermal constraints

(17:27) What's accelerating now: UCIe adoption, cross-chain collaboration, photonics, and advanced packaging

More about this episode...

In this Season 3 premiere of the Siemens 3D IC Podcast, new host Tova Levy speaks with Archana Cheruliyil, Principal Product Marketing Manager at Alphawave Semi, a Qualcomm company, about what it really takes to develop IP for 3D ICs — and why connectivity has shifted from a background function to a system-defining one. Alphawave Semi's portfolio spans UCIe die-to-die interconnect, HBM memory interfaces, PCIe, CXL, and custom silicon, all optimized for the disaggregated architectures that 3D IC design demands.

Archana places connectivity IP at the center of the challenge: in stacked, chiplet-based designs, the interconnect layer directly determines system performance, power efficiency, and scalability. Signal integrity behaves differently in dense 3D electromagnetic environments, power delivery must be managed vertically across multiple dies, and thermal hotspots in stacked logic have no easy escape path — forcing teams into system-level trade-offs across signal, power, thermal, and packaging simultaneously. Adding photonics into the mix raises the stakes further, combining different materials and design constraints within the same package.

On the market side, Archana unpacks the tension between open standards like UCIe — which enable interoperability but can't always keep pace with customer demands — and the highly customized solutions that drive real differentiation. Siemens is highlighted as a key emulation and system-level validation partner, helping teams understand full-system behavior before silicon is produced.

The episode closes with Archana's vision for what would unlock the next phase of 3D IC adoption: a truly open chiplet marketplace that frees engineering cycles for innovation rather than integration reinvention — and progress on thermal management to enable deeper stacking across a broader range of applications.

Ideal for: 3D IC architects, silicon IP designers, advanced packaging engineers, chiplet ecosystem participants, EDA users, and anyone navigating the shift from monolithic SoC design to heterogeneous, disaggregated integration.

Connect with Tova Levy

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Website

Connect with Archana P Cheruliyil

LinkedIn

Alphawave’s website

How do you transition from today’s 2.5D systems into tomorrow’s true 3D IC architectures — while balancing cost, performance, and thermal demands?

What you’ll learn…

Where hyperscalers and AI accelerator developers are leading the 3D IC adoption curve.

Why design enablement and ecosystems are still evolving for mainstream adoption.

The tipping points that push companies toward 2.5D/3D IC designs.

The new methodology requirements: system-centric, predictive, shift-left modeling.

Why siloed design teams can’t meet the demands of advanced 3D IC.

How Siemens’ portfolio and AE expertise help customers adapt tools, methods, and organizations for success.

What you’ll discover…

(01:40) Current state of 3D IC adoption: hyperscalers, AI accelerators, and beyond.

(04:20) 3D VS 2.5D design and (hybrid bonding, stacking, bridges).

(05:30) Why customers want to learn more about 3D IC design.

(06:50) Why do customers move over to 3D IC design?

(08:25) Challenges in 3D IC design.

(10:20) Methodology shifts: early system-level planning and predictive modeling

(13:30) Siemens’ broad portfolio, roadmap collaboration, and multi-physics modeling

(15:45) The 5-year outlook: chiplet standards, system-on-wafer, and power/thermal battles

More about this episode…

In this episode of the Siemens 3D IC Podcast, host John McMillan speaks with Kevin Rinebold, 3D IC Packaging and Account Technology Manager at Siemens EDA. With over 35 years of customer-facing experience, Kevin shares insights into the evolution of advanced packaging, chiplet integration, and the methodologies needed for the next wave of 3D IC adoption.

The discussion covers how hyperscalers are driving AI and high-performance compute with 2.5D and emerging 3D approaches, why design enablement remains uneven across the supply chain, and what’s required to balance thermal, power, and signal considerations at scale. Kevin emphasizes that 3D IC isn’t just a technical challenge; it’s an organizational shift toward integrated, cross-disciplinary collaboration.

He also highlights Siemens’ role in enabling customers to “shift left,” evaluate tradeoffs early, and leverage a broad portfolio of tools and expertise to meet the complexity of future 3D IC designs. Looking ahead, Kevin points to maturing chiplet standards, system-on-wafer architectures, and the ongoing battle to get power in and heat out of dense 3D IC stacks.

Ideal for: IC packaging engineers, 3D IC architects, chiplet designers, substrate fabricators, and verification professionals navigating the shift from 2.5D to 3D integration.

Connect with John McMillan

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Website

Connect with Kevin Rinebold

LinkedIn

Website

How do you ensure that cutting-edge 3D IC designs can actually be manufactured before investing millions in production?

What you’ll learn…

What test vehicles are and why they’re indispensable for validating manufacturability

How daisy chain structures pinpoint weaknesses in bumps, balls, and die connections

Who builds test vehicles: OSATs, foundries, or customers, and why it matters

How test vehicles strengthen collaboration between OEMs and OSATs

The hidden value of test vehicles in reliability, regulatory compliance, and risk mitigation

Where you’ll find it….

(02:00) What a test vehicle is when it’s needed

(03:20) Real-world example: testing embedded chips before mass production

(06:00) Who’s responsible for creating test vehicles?

(07:20) How do test vehicles factor into the relationship between the OSATs and the OEMs?

(09:25) The link between test vehicles and PCB design practices

(11:12) Beyond connectivity: heaters, capacitive structures, and stacked vias

(15:25) Automotive and regulatory requirements for reliability testing

(17:15) Why engineers shouldn’t design daisy chains by hand

More about this episode…

In this episode of the Siemens 3D IC Podcast, host John McMillan talks with Kendall Hiles, Senior 3D IC Product Specialist at Siemens EDA, about the critical role of test vehicles and daisy chain design tests in semiconductor innovation.

Unlike a final product, a test vehicle isn’t built to sell, it’s built to learn. Kendall Hiles explains how test vehicles act as manufacturing “test beds,” enabling engineers to validate new processes and technologies before scaling up to costly production runs.

The conversation dives into daisy chain design tests, a clever way of stringing together bumps and balls to measure connectivity and identify failure points with precision. Kendall also highlights when OSATs, foundries, or customers should take ownership of creating test vehicles, and how they factor into collaboration between OEMs and manufacturers.

Listeners will also hear why test vehicles are especially vital for automotive reliability and regulatory compliance, and why manual spreadsheet-driven daisy chain design is a risky practice in today’s complex 3D IC world.

For anyone working in semiconductor packaging, 3D IC design, or advanced manufacturing, this episode offers practical insight into improving yield, reducing risk, and accelerating innovation.

Connect with John McMillan

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Website

Connect with Kendall Hiles

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Website

How do you design and verify a package with tens of millions of pins — without losing months to manual rework?

What you’ll learn…

Why chiplet-based architectures demand new approaches to IC packaging

How hierarchical device planning reduces overwhelming complexity

The risks of spreadsheet-based workflows and why they’re no longer viable

How early, multi-domain analysis helps avoid costly late-stage redesigns

What Siemens’ Innovator 3D IC Portfolio offers for synchronized, error-proof design

Where you’ll find it….

(01:50) Current changes in IC Packaging and the impact on the whole ecosystem 

(03:00) How to manage complexity scaling 

(03:35) What hierarchical device planning is and why it matters 

(05:00) How traditional methods fall short for high-pin-count designs 

(06:20) The risks and consequences of package assembly errors 

(07:00) What next-gen tools must deliver for designers 

(09:10) Siemens’ Innovator 3D IC Portfolio overview 

More about this episode…

In this episode of the Siemens 3D IC Podcast, host John McMillan speaks with Per Viklund, Director of IC Packaging and RF Product Lines at Siemens EDA, about the growing challenge of managing chiplet and interposer complexity in advanced 3D IC designs.

Per explains how hierarchical device planning enables designers to work at the right level of abstraction, streamlining the creation, optimization, and verification of massive, high-pin-count packages. The discussion covers why spreadsheet-based methods no longer cut it, the risks of unsynchronized workflows, and how early, multi-domain analysis can prevent costly late-stage redesigns.

The episode also introduces Siemens’ Innovator 3D IC Portfolio — a unified, AI-infused solution designed to support the entire packaging workflow, from early planning through final layout, with built-in data management to eliminate version errors.

Ideal for IC packaging engineers, 3D IC architects, chiplet designers, substrate fabricators, and verification professionals working on high-complexity designs.

Connect with John McMillan

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Website

Connect with Per Viklund

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Website