Welcome Joren Vaes, design engineer at SOFICS
Simulation is critical when designing analog devices based on a PDK from the fabParasitics are significant, especially with new nodes having upwards of 16 metal layersChris complained about a class where the professor made them draw planar structures with graph paper with colored pencilsLarge fabs on leading edge nodes have 1800 page textbook of rulesBecause the constraints get tighter, that book gets longer for each node2 nm mass production on finfet currently with TSMC22 was the last classic cmosFinfet, looks like a devil‘gate all around’ / nanosheetCFET (complementary field effect transistor) is nextJoren really gets Maxwells Equations…as you have to at super high speedsSOFICS are making phy’s / IP blocksAmplifiers that are DC to 50 GHzMaking a datasheet for the resulting IP blockJoren got his PhD working on millimeter wave applicationsIt’s all just physicsUsing coils to impedance match between layersReflecting off of different materials at angles is Snells law (not lorentz equation) and that extends to different materials at different wavelengthsCables are very lossy at 100 GHz…dBs per cmParasitics impact every part of the design processWireline community – name for the high speed interfaces, including research in the spaceMost transistor threshhold voltages that Joren works with are … 750 mV!Voltage dependent drc rulesElectromigration – holes in wires from electronsESD is a big part of the business, and a large source of parasiticsNew product development for IP blocksWorking with customers and Foundry at the 2 nm nodeDesign companies need to be paying 100s of thousands to software providersAfter, it goes to spice and schedmaticJoren decides whether to jump in on layoutLVS – layout vs schematicParasitic extraction (spice netlist)PDKs define how you can do the layout stageLower cost tools exist but more expensive tools have tooling that tells you when you’re violating DRC3 main vendorsCadenceSynopsisSiemens (Calibre)Foundries soemtimes only support one toolDoing test wafers allows testing of structures. They often get MPW at a discount from the fab (since they’re often testing new processes as well)How do they test with packaging options?‘low speed’ can be die bonded or pcb mountedhigh speed does on wafer probing (with veeeery expensive probes)Check out Sofics.com for more info on the company. They also have a blog with a great name.Follow or connect with Joren on LinkedIn