Welcome James Adams, Chris Boross, Liam Fraser, and Luke Wren!
The last time the RPi team was on the show was about the RP1 (#648)The order of parts being released was RP2040->RP1->RP2350Check out the datasheet for the RP2350Learning from siliconSecurity and power statesThe part is a “Dual dual core”The Arm side is a Dual M33The RISC V side is a Hazard 3 processor, designed by Luke based on a previous processor called the Hazard 5HB5There is a mux on the core and you select which side you’re going to use at bootThere are 48 GPIO (but users always want more)Chris Boross (first time on the show) is on the commercial team. He’s seing interesting applications for the RP2350 including devices that are using it for motor control.They also have seen the part used in satellites because mRAM or masked ROM is less susceptible to radiation errorsThe PIOs have changed, but are more evolutionary from the RP2040The PIO allows you to create state machines that process inputs without processor interventions, basically like tiny cores2 cores – 8 totalInteresting PIO applicationsLuke still likes that DVI on 2040 that was discussed on the first episode they were on (#529)CAN is possibleUSB host / deviceMII / RMIIULPI – USB 2.0 PhyThe core frequency only increased 133 MHz -> 150 MHz. There is tougher timing with the M33LVT – lower voltage threshhold30 -> 40 pinsThere are now variants listed on the RP2350 product page (but not in mass production) that include flash in the SOM packageRP2040 was one power domain“Powerman” (and of course AVR Man)Switched coreAON – always on32 kHzThere is a C/C++ SDK that is the basis for other portsSecurity is a focus for the RP2350Bootrom in every chipSecure bootM33 features – secure / non-secureRISC V PMPRCP – Redundancy CoprocessorRaspberry Pi had a challenge / bounty for getting the secret out of the RP2350 OTP with secure bootOne of the few silicon companies doing this sort of thing in publicPast guest Aedan Cullen was one of the hacks called “Hazardous threes”. He gave a talk about it at 38C3Past guest Colin O’Flynn was also mentioned because collaboration around side channel attacks with the Chip WhispererIOActive used a FIB – Fine Ion Beam – and passive voltage contrast to capture an impressive image of a decapped chip (see the RPi post)“Never want to see ‘novel technique’ in an email”Improving the RP2350 siliconHow do you decide what to fix/leave?Can it be changed in metal/vias?SIO spinlock not being fixedChicken BitFiller cells are reprogrammable and help with fixesIt costs approximately $50K per layer to change (ostensibly because of the high costs of masks)ULA – uncommitted logic arrayDie shrink doesn’t seem to make senseWill keep making each chip as long as 40 nm fabs are aroundThinking about the RP2040The easiest way to get started is to use a Pico (RP2040) or a Pico 2 (RP2350). Both have connectivity options as well.Raspberry Pi is now a public company! Doesn’t change much other than the business scrutiny.