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In this episode of the Embedded Edge podcast, we talk to industry veteran John Goodacre about an initiative he is leading to make computer systems architecture more ‘secure by design’ by addressing memory safety exploits. This involves use of the CHERI-enabled RISC processors that are gaining significant academic and industrial interest.
By AspenCoreIn this episode of the Embedded Edge podcast, we talk to industry veteran John Goodacre about an initiative he is leading to make computer systems architecture more ‘secure by design’ by addressing memory safety exploits. This involves use of the CHERI-enabled RISC processors that are gaining significant academic and industrial interest.

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