Dr. Partha Ranganathan is a VP and Technical Fellow at Google, where he serves as the area technical lead for hardware and datacenters. Partha is currently driving next-generation computing systems for the AI era, tackling the challenges of building, scaling and managing warehouse-scale computers, and the bleeding edge of hardware-software codesign. He has pioneered numerous impactful innovations touching billions of users--spanning power-efficient servers, specialized accelerators, and disaggregated datacenters. A leading voice in the field, Partha has published 100+ papers, is a co-inventor on 125+ patents, and co-authored the seminal textbook, "The Datacenter as a Computer." He is an IEEE and ACM Fellow, a member of the ISCA, ASPLOS, HPCA halls of fame, a recipient of the ACM SIGARCH Maurice Wilkes Award, MIT Tech Review's top-35 young innovators, distinguished alumni awards from Rice University and IIT Madras, and uniquely for a computer scientist, an Emmy Award.

Dr. Tushar Krishna is an Associate Professor in the School of Electrical and Computer Engineering at Georgia Tech, who holds a Ph.D. from MIT. Tushar’s work shapes how the computing community designs modern large-scale distributed AI systems--spanning specialized accelerators, memory hierarchies, and communication fabrics--and driving design-space exploration with pioneering tools like ASTRA-sim, Chakra, and Garnet. A member of the ISCA, MICRO, and HPCA Halls of Fame, his impactful research has garnered over 21,000 citations and the 2025 DAC "Under 40 Innovators Award." He also actively shapes future AI computing standards as the Co-director of Georgia Tech's CRNCH and co-chair of the MLCommons Chakra Working Group.

Dr. Babak Falsafi is a Professor at EPFL, the founding president of the Swiss Data Center Efficiency Association, and the founder of EcoCloud, an academic consortium focused on sustainable IT. His contributions to computer architecture include the invention of spatial and temporal memory streaming (SMS prefetchers) found in ARM cores and laying the groundwork for fence speculation by defining memory ordering requirements in modern CPUs. He is a key figure in cloud-native server design, with his work forming the foundation for the first-generation Cavium ARM server CPUs. He is a former chair of the SIGARCH Executive Committee, a recipient of the Alfred P. Sloan Research Fellowship and a Fellow of both the ACM and IEEE.

Dr. Caroline Trippel is an Assistant Professor in the Computer Science and Electrical Engineering Departments at Stanford University. Caroline's research operates at the critical intersection of hardware and software, focusing on developing high-assurance computer architectures. Her work tackles the challenge of ensuring that complex hardware designs are correct and secure. She has pioneered automated tools that bridge the gap between a processor's implementation (its RTL) and its formal specification, as well as frameworks and compilers that find and mitigate hardware-related security vulnerabilities in software.

Dr. Ricardo Bianchini is a Technical Fellow and Corporate Vice President at Microsoft Azure, where he leads the team responsible for managing Azure’s compute workload, server capacity, and datacenter infrastructure with a strong focus on efficiency and sustainability.  Before joining Azure, Ricardo led the Systems Research Group and the Cloud Efficiency team at Microsoft Research (MSR). He created research projects in power efficiency and intelligent resource management that resulted in large-scale production systems across Microsoft. Prior to Microsoft, he was a Professor at Rutgers University, where he conducted research in datacenter power and energy management, cluster-based systems, and other cloud-related topics. Ricardo is a Fellow of both the ACM and IEEE.

Dr. Arkaprava Basu is an Associate Professor at the Indian Institute of Science, where he mentors students in the Computer Systems Lab. Arka's research focuses on pushing the boundaries of memory management and software reliability for both CPUs and GPUs. His work spans diverse areas, from optimizing memory systems for chiplet-based GPUs to developing innovative techniques to eliminate synchronization bottlenecks in GPU programs. He is also a recipient of the Intel Rising Star Faculty Award, ACM India Early Career Award,  and multiple other accolades, recognizing his innovative approaches to enhancing GPU performance, programmability, and reliability.

Dr. Dan Sorin is a Professor of Electrical and Computer Engineering at Duke University, and a co-founder of Realtime Robotics. Dan is widely known for his pioneering work in memory systems. He has co-authored the seminal Primer on Memory Consistency and Cache Coherence, which has become a foundational resource for students and researchers alike. Dan’s contributions span from developing resilient systems that tolerate hardware faults to innovations in cache coherence protocols, and has been recognized by multiple best paper awards and patents. His work at Realtime Robotics has pushed the boundaries of autonomous motion planning, enabling real-time decision-making in dynamic environments.

Dr. Vijay Janapa Reddi is an Associate Professor at Harvard University, and Vice President and Co-founder of MLCommons. He has made substantial contributions to mobile and edge computing systems, and played a key role in developing the MLPerf Benchmarks. Vijay has authored the machine learning systems book mlsysbook.ai, as part of his twin passions of education and outreach. He received the IEEE TCCA Young Computer Architect Award in 2016, has been inducted in the MICRO and HPCA Halls of Fame, and is a recipient of multiple best paper awards. 

Dr. Carole-Jean Wu is a Director of AI Research at Meta. She is a founding member and a Vice President of MLCommons – a non-profit organization that aims to accelerate machine learning innovations for the benefits of all. Dr. Wu also serves on the MLCommons Board as a Director, chaired the MLPerf Recommendation Benchmark Advisory Board, and co-chaired for MLPerf Inference. Prior to Meta/Facebook, Dr. Wu was a professor at ASU. She earned her M.A. and Ph.D. degrees in Electrical Engineering from Princeton University and a B.Sc. degree in Electrical and Computer Engineering from Cornell University.  Dr. Wu’s expertise sits at the intersection of computer architecture and machine learning. Her work spans across datacenter infrastructures and edge systems, such as developing energy- and memory-efficient systems and microarchitectures, optimizing systems for machine learning execution at-scale, and designing learning-based approaches for system design and optimization. She is passionate about pathfinding and tackling system challenges to enable efficient and responsible AI technologies.

Dr. Karu Sankaralingam is a Professor at the University of Wisconsin-Madison, an entrepeneur, inventor, as well as a Principal Research Scientist at NVIDIA.  His work has been featured in industry forums of Mentor and Synopsys, and has been covered by the New York Times, Wired, and IEEE Spectrum. He founded the hardware startup SimpleMachines in 2017 which developed chip designs applying dataflow computing to push the limits of AI generality in hardware and built the Mozart chip. In his career, he has led three chip projects: Mozart (16nm, HBM2 based design), MIAOW open source GPU on FPGA, and the TRIPS chip as a student during his PhD. In his research he has pioneered the principles of dataflow computing, focusing on the role of architecture, microarchitecture and the compiler. He has published over 100 research papers, has graduated 9 PhD students, is an inventor on 21 patents, and 9 award papers. He is a Fellow of IEEE.