Condor Currents

## Episode Summary

In this episode, we cover:

- **FlashAccel: Leveraging High-Bandwidth Flash for High-Throughput LLM Inference** (arXiv)

- **IRONSmith: A Visual Dataflow Design Environment for AMD Ryzen AI NPUs** (arXiv)

- **SpacemiT to launch server-class RISC-V processor following capital injection - South China Morning Post** (google_riscv)

- **Milk-V Jupiter2 is mini PC with a SpacemiT K3 RISC-V processor - Liliputing** (google_riscv)

- **AI is stress-testing processor architectures and RISC-V fits the moment - EDN - Voice of the Engineer** (google_riscv)

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*Sponsored by LimitLess AI*

## Episode Summary

In this episode, we cover:

- **STEEL: Sparsity-Aware Fused Attention for Energy-Efficient Long-Sequence Inference on AMD's XDNA NPU** (arXiv)

- **StreamDQ: Near-Memory Weight DeQuantization in Custom HBM for Scalable AI Inference Acceleration** (arXiv)

- **Security Researchers Find Current RISC-V CPU Implementations Coming Up Short - Phoronix** (google_riscv)

- **SiFive Upgrades P500 RISC-V IP Cores - embedded.com** (google_riscv)

- **Vividnode Mobile AI Packs RISC-V Processor and 60 TOPS AI Engine - LinuxGizmos.com** (google_riscv)

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*Sponsored by LimitLess AI*

## Episode Summary

In this episode, we cover:

- **Embedded Blockchain Infrastructure Management (eBIM): A RISC-V-Empowered Hardware--Software Co-Design Framework Towards Trustworthy Blockchain** (arXiv)

- **Auto-DSM Under the Lens: A Black-Box Evaluation Framework for LLM-Based DSM Generation** (arXiv)

- **India Launches DHRUV64, Its First 1 GHz, 64-bit Dual-Core RISC-V CPU - TechPowerUp** (google_riscv)

- **Prompt to tape out: Autonomous AI agent builds 1.5 GHz RISC-V CPU - Adafruit** (google_riscv)

- **The next RISC-V processor frontier: AI - EDN - Voice of the Engineer** (google_riscv)

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*Sponsored by LimitLess AI*

## Episode Summary

In this episode, we cover:

- **HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing** (arXiv)

- **ATLAS: Automated HLS for DL-Optimized FPGAs** (arXiv)

- **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - Business Wire** (google_riscv)

- **India unveils a homegrown dual-core 1GHz RISC-V processor, the DHRUV64 - The Register** (google_riscv)

- **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - TechPowerUp** (google_riscv)

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*Sponsored by LimitLess AI*

## Episode Summary

In this episode, we cover:

- **Vectorizing Quantum Control: A RISC-V Vector Extension Architecture for Scalable Qubit Systems** (arXiv)

- **Memory Scarcity, Open Models, and the Restructuring of the AI Industry, 2026-2030 -- A quantitative scenario analysis of inference economics, training-cost divergence, and infrastructure solvency** (arXiv)

- **RISC-V Vector Engine Addresses 128 Qubits With One Instruction - Quantum Zeitgeist** (google_riscv)

- **The RISC-V Vector Extensions for AI - Jon Peddie Research** (google_riscv)

- **China's LineShine tops supercomputer ranking with all-CPU architecture - China Daily** (google_arch)

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*Sponsored by LimitLess AI*

## Episode Summary

In this episode, we cover:

- **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_arch)

- **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - AOL.com** (google_riscv)

- **How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours - IEEE Spectrum** (google_riscv)

- **Zhihe A210 octa-core RISC-V SoC with 12 TOPS NPU powers SoM-based development board - CNX Software** (google_riscv)

- **Modder builds 8,192-core GPU at home out of RISC-V microcontrollers — full "graphics card" draws over 2,000 watts of power, requires a 3D printer to program - Tom's Hardware** (google_riscv)

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*Sponsored by LimitLess AI*

## Episode Summary

In this episode, we cover:

- **TileLens: Efficiently Using Large-Granularity Memory Systems with Transparent Two-Dimensional Memory Layout** (arXiv)

- **Bounded-Memory Parallel Image Pulling for Large Container Images** (arXiv)

- **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on Board - TechPowerUp** (google_arch)

- **Deja Vu: A Brief History of Every Mac CPU Architecture - How-To Geek** (google_arch)

- **Arm Neoverse CMN-700: Performance Analysis Methodology** (semiengineering)

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*Sponsored by LimitLess AI*

## Episode Summary

In this episode, we cover:

- **A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration** (arXiv)

- **ELiTeFormer: An Efficient Transformer for FPGAs** (arXiv)

- **The key CPU architecture you've never heard of: RISC-V - RedShark News** (google_arch)

- **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - Phoronix** (google_riscv)

- **Memory wall: Why cache miss tolerance defines CPU performance now - EDN - Voice of the Engineer** (google_riscv)

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*Sponsored by LimitLess AI*

## Episode Summary

In this episode, we cover:

- **A Multi-Dimensional, Per-Pass Empirical Study of the LLVM Optimization Pipeline** (arXiv)

- **Approximate Attention Weighting for Sustainable FPGA-Based Vision Transformer Inference** (arXiv)

- **Performance aware shared memory hierarchy model for multicore processors - Nature** (google_arch)

- **RISC-V vs ARM: Which Instruction Set Architecture Will Dominate the Future? - Electropages** (google_arch)

- **Bit-Brick K1: Raspberry Pi 5 alternative with different CPU architecture, M.2 and PCIe support launches - Notebookcheck** (google_arch)

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*Sponsored by LimitLess AI*

## Episode Summary

In this episode, we cover:

- **The Fourth-Root Complexity of Data Movement** (arXiv)

- **Dynamic Ultrasound Beamforming Using Left-to-Right Arithmetic Adders on FPGA** (arXiv)

- **Migration Using Context Cache for Multicore RISC‐V Processor - Wiley Online Library** (google_riscv)

- **QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System Stacks - IEEE Computer Society** (google_arch)

- **NextSilicon Productizes Arbel RISC-V Core Into 64-Core Enterprise Processor - Quantum Zeitgeist** (google_riscv)

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*Sponsored by LimitLess AI*