Condor Currents

Condor Currents

By Condor ComputingTechnologyTech News
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Condor Currents episodes

  • CrossPool: Efficient Multi-LLM Serving for Cold MoE Models through KV-Cache and Weight Disaggregation
    ## Episode Summary
    In this episode, we cover:
    - **CrossPool: Efficient Multi-LLM Serving for Cold MoE Models through KV-Cache and Weight Disaggregation** (arXiv)
    - **2.5D Root of Trust: Securing the Chiplet Ecosystem** (arXiv)
    - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_arch)
    - **Zhihe A210 octa-core RISC-V SoC with 12 TOPS NPU powers SoM-based development board - CNX Software** (google_riscv)
    - **How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours - IEEE Spectrum** (google_riscv)
    ---
    *Sponsored by LimitLess AI*
    17 min
  • Non-Uniform L2 Cache Latency Across the Streaming Multiprocessors of an NVIDIA L40
    ## Episode Summary
    In this episode, we cover:
    - **Non-Uniform L2 Cache Latency Across the Streaming Multiprocessors of an NVIDIA L40** (arXiv)
    - **MOCAP: Wafer-Scale-Chip-Oriented Memory-Orchestrated Chunked Pipelining Framework for Prefill-Only LLM Inference** (arXiv)
    - **Software to Silicon With RISC-V for Physical AI** (eetimes)
    - **Deja Vu: A Brief History of Every Mac CPU Architecture - How-To Geek** (google_arch)
    - **Synergy Quantum Unveils Quantum-Safe Silicon IP Cores for RISC-V-Based SoCs - Yahoo Finance** (google_riscv)
    ---
    *Sponsored by LimitLess AI*
    17 min
  • UltraQuant: 4-bit KV Caching for Context-Heavy Agents
    ## Episode Summary
    In this episode, we cover:
    - **UltraQuant: 4-bit KV Caching for Context-Heavy Agents** (arXiv)
    - **Fractional Verkle Trees: A Hypertree Decomposition and Verified Proof Serialization Architecture for High-Performance Blockchain State Accumulators** (arXiv)
    - **The key CPU architecture you've never heard of: RISC-V - RedShark News** (google_arch)
    - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - Phoronix** (google_riscv)
    - **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on Board - TechPowerUp** (google_arch)
    ---
    *Sponsored by LimitLess AI*
    17 min
  • Low-Energy Reduced RISC-V Instruction Subset Processor for Tsetlin Machine Inference at the Edge
    ## Episode Summary
    In this episode, we cover:
    - **Low-Energy Reduced RISC-V Instruction Subset Processor for Tsetlin Machine Inference at the Edge** (arXiv)
    - **From the NYU Ultracomputer to Modern Exascale: A Historical and Architectural Survey of In-Network Computing and Scalable Synchronization** (arXiv)
    - **Performance aware shared memory hierarchy model for multicore processors - Nature** (google_arch)
    - **RISC-V vs ARM: Which Instruction Set Architecture Will Dominate the Future? - Electropages** (google_arch)
    - **Bit-Brick K1: Raspberry Pi 5 alternative with different CPU architecture, M.2 and PCIe support launches - Notebookcheck** (google_arch)
    ---
    *Sponsored by LimitLess AI*
    15 min
  • AIA: A Customized Multi-core RISC-V SoC for Discrete Sampling Workloads in 16 nm
    ## Episode Summary
    In this episode, we cover:
    - **AIA: A Customized Multi-core RISC-V SoC for Discrete Sampling Workloads in 16 nm** (arXiv)
    - **AIA: A 16nm Multicore SoC for Approximate Inference Acceleration Exploiting Non-normalized Knuth-Yao Sampling and Inter-Core Register Sharing** (arXiv)
    - **Migration Using Context Cache for Multicore RISC‐V Processor - Wiley Online Library** (google_riscv)
    - **The Evolution of CPU Architectures – From Intel 4004 To Modern SoCs - Wccftech** (google_arch)
    - **QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System Stacks - IEEE Computer Society** (google_arch)
    ---
    *Sponsored by LimitLess AI*
    14 min
  • SMEPilot: Characterizing and Optimizing LLM Inference with Scalable Matrix Extensions
    ## Episode Summary
    In this episode, we cover:
    - **SMEPilot: Characterizing and Optimizing LLM Inference with Scalable Matrix Extensions** (arXiv)
    - **The Price of Anarchy in Disaggregated Inference** (arXiv)
    - **RISC-V Mentorship Taught Me the RISC-V ISA Is Far More Than a Reference Manual** (riscv_news)
    - **One ISA, Infinite Use Cases: RISC-V and the Road to Workload-Specific Silicon** (riscv_news)
    - **RISC-V set to announce 25% market penetration — open-standard ISA is ahead of schedule, securing fast-growing silicon footprint - Tom's Hardware** (google_riscv)
    ---
    *Sponsored by LimitLess AI*
    18 min
  • A Spatio-Temporal Expert Prefetching Framework for Efficient MoE-based LLM Inference
    ## Episode Summary
    In this episode, we cover:
    - **A Spatio-Temporal Expert Prefetching Framework for Efficient MoE-based LLM Inference** (arXiv)
    - **MADAR: An Address-Free Processor** (arXiv)
    - **Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday** (google_arch)
    - **Support RAJA and Scientific Applications on RVV Architectures** (riscv_news)
    - **Synergy Quantum Unveils Quantum-Safe Silicon IP Cores for RISC-V-Based SoCs - PR Newswire** (google_riscv)
    ---
    *Sponsored by LimitLess AI*
    0 min
  • Tiara: A Programmable Line-Rate ISA for Remote Memory Access
    ## Episode Summary
    In this episode, we cover:
    - **Tiara: A Programmable Line-Rate ISA for Remote Memory Access** (arXiv)
    - **HierSVA: A Data Synthesis Pipeline, Dataset, and Benchmark for LLM-Driven Hierarchical Hardware Formal Verification** (arXiv)
    - **Using a Performance Model to Implement a Superscalar CVA6** (riscv_news)
    - **Ben C.'s Clever Compiler Imports Verilog Designs, Including a Working RISC-V CPU, Into Factorio - Hackster.io** (google_riscv)
    - **Now you can put a SpacemiT K3 RISC-V processor in a Framework Laptop 13 - Liliputing** (google_riscv)
    ---
    *Sponsored by LimitLess AI*
    15 min
  • Isolation-aware Scheduling Framework for DNN-based End-to-End Autonomous Driving System on Tile-based Accelerators
    ## Episode Summary
    In this episode, we cover:
    - **Isolation-aware Scheduling Framework for DNN-based End-to-End Autonomous Driving System on Tile-based Accelerators** (arXiv)
    - **Non-Parametric Dual-Manifold Mapping via 8-Bit Bounded Transformation Matrices: Challenging FP-centric Hardware Paradigms in Low-Energy AI** (arXiv)
    - **160-core RISC V Board Is The M.2 CoProcessor You Didn’t Know You Needed - Hackaday** (google_riscv)
    - **Microchip Upgrades Its Mi-V RV32 RISC-V Soft-Core Processor, Promises a Major Speed Boost - Hackster.io** (google_riscv)
    - **SpacemiT to launch server-class RISC-V processor following capital injection - South China Morning Post** (google_riscv)
    ---
    *Sponsored by LimitLess AI*
    15 min
  • Energy-Efficient On-Device RAG on a Mobile NPU: System Design and Benchmark on Snapdragon X Elite
    ## Episode Summary
    In this episode, we cover:
    - **Energy-Efficient On-Device RAG on a Mobile NPU: System Design and Benchmark on Snapdragon X Elite** (arXiv)
    - **A Hybrid Edge-Cloud Architecture for Low-Latency Entitlement Verification in Resource-Constrained Devices** (arXiv)
    - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - TechPowerUp** (google_riscv)
    - **Security Researchers Find Current RISC-V CPU Implementations Coming Up Short - Phoronix** (google_riscv)
    - **AI is stress-testing processor architectures and RISC-V fits the moment - EDN - Voice of the Engineer** (google_riscv)
    ---
    *Sponsored by LimitLess AI*
    13 min

About Condor Currents

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Condor Currents delivers concise breakdowns of the latest computer architecture research and RISC-V developments. Each episode covers recent arXiv papers on data prefetching, branch prediction, and…