Condor Currents

Condor Currents

By Condor ComputingTechnologyTech News
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Condor Currents episodes

  • What Actually Serializes GPU LZ77 Decode: Three Decoders, Three Mechanisms, and an Encode-Time Lever That Removes the Last One
    ## Episode Summary
    In this episode, we cover:
    - **What Actually Serializes GPU LZ77 Decode: Three Decoders, Three Mechanisms, and an Encode-Time Lever That Removes the Last One** (arXiv)
    - **ARMOR: Accelerating RTL Simulation by Mitigating the Front-End Bottleneck Using Node Compression** (arXiv)
    - **SpacemiT K3 “16-core” RISC-V SoC system information and (early) benchmarks - cnx-software.com** (google_riscv)
    - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - Phoronix** (google_riscv)
    - **The Evolution of CPU Architectures – From Intel 4004 To Modern SoCs - Wccftech** (google_arch)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    17 min
  • SLAC: Access-Driven CPU-to-GPU Side-channel Attacks via System-Level Cache on Apple Silicon
    ## Episode Summary
    In this episode, we cover:
    - **SLAC: Access-Driven CPU-to-GPU Side-channel Attacks via System-Level Cache on Apple Silicon** (arXiv)
    - **DistillCache: KL-Guided Adaptive KV-Cache Eviction for Memory-Efficient LLM Inference** (arXiv)
    - **A Deep Dive Into CPU Architecture - i-programmer.info** (google_arch)
    - **How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours - IEEE Spectrum** (google_riscv)
    - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - Business Wire** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    15 min
  • Why Do Prefetchers Fail? Let Agents Answer
    ## Episode Summary
    In this episode, we cover:
    - **Why Do Prefetchers Fail? Let Agents Answer** (arXiv)
    - **Machine Shape and Hierarchical Blocking: A Mathematics of Arrays Formalization, with an Open Problem in Hierarchical Shape Occupancy** (arXiv)
    - **Checking In On The ISA Wars And Its Impact On CPU Architectures - hackaday.com** (google_arch)
    - **China's LineShine tops supercomputer ranking with all-CPU architecture - chinadaily.com.cn** (google_arch)
    - **QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System Stacks - computer.org** (google_arch)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    0 min
  • APEX: Adaptive Expert Prefetching for Memory-Efficient Edge MoE Inference
    ## Episode Summary
    In this episode, we cover:
    - **APEX: Adaptive Expert Prefetching for Memory-Efficient Edge MoE Inference** (arXiv)
    - **Aneto: Predicting System Performance by Exploiting Cross-Workload Regularity** (arXiv)
    - **RISC-V: The Open-Source Revolution in CPU Architecture - design-reuse.com** (google_arch)
    - **Conflict to Compliance: RISC-V Extension Migration Across Spec, HW, and SW** (riscv_news)
    - **China's LineShine tops supercomputer ranking with all-CPU architecture - China Daily** (google_arch)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    0 min
  • ArchAgent v2: A Case Study with the Data Prefetching Championship
    ## Episode Summary
    In this episode, we cover:
    - **ArchAgent v2: A Case Study with the Data Prefetching Championship** (arXiv)
    - **The Fallacy of Independent Ceilings: Characterizing Coupled Load-Branch Stall Interaction** (arXiv)
    - **Migration Using Context Cache for Multicore RISC‐V Processor - onlinelibrary.wiley.com** (google_riscv)
    - **Chinese Loongson processors have leaky caches, researchers find** (the_register)
    - **Spectre rears its ugly head again as researchers show some RISC-V chips are susceptible** (the_register)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    21 min
  • A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs
    ## Episode Summary
    In this episode, we cover:
    - **A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs** (arXiv)
    - **MCHA: A Memory-Centric Hierarchical Architecture for Parallel-Sequential Computing** (arXiv)
    - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_arch)
    - **Evaluating and Calibrating Performance On RISC-V Vector Processors (KTH, LLNL, BSC) - semiengineering.com** (google_riscv)
    - **The RISC-V Vector Extensions for AI - Jon Peddie Research** (google_riscv)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    17 min
  • Heterogeneous LLM Serving with General-Purpose Processing-Near-Memory for Retrieval-Based Sparse Attention
    ## Episode Summary
    In this episode, we cover:
    - **Heterogeneous LLM Serving with General-Purpose Processing-Near-Memory for Retrieval-Based Sparse Attention** (arXiv)
    - **Celty: SpMspV GPU Kernel and SIMT Co-Design for Efficient Dual-Sparse LLM Inference** (arXiv)
    - **Bit-Brick K1: Raspberry Pi 5 alternative with different CPU architecture, M.2 and PCIe support launches - notebookcheck.net** (google_arch)
    - **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on Board - TechPowerUp** (google_arch)
    - **Deja Vu: A Brief History of Every Mac CPU Architecture - How-To Geek** (google_arch)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    16 min
  • PLoRA: An NDP-Enhanced Pooled-Memory System for Cost-Efficient Multi-LoRA Serving
    ## Episode Summary
    In this episode, we cover:
    - **PLoRA: An NDP-Enhanced Pooled-Memory System for Cost-Efficient Multi-LoRA Serving** (arXiv)
    - **Breaking Memory Bottlenecks in Quantum Control Systems for More Precise Experiments and Higher Throughput Computing** (arXiv)
    - **SpacemiT K3 “16-core” RISC-V SoC system information and (early) benchmarks - CNX Software** (google_riscv)
    - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - phoronix.com** (google_riscv)
    - **Performance aware shared memory hierarchy model for multicore processors - nature.com** (google_arch)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    17 min
  • Architectural Implications of Agentic AI Workflows
    ## Episode Summary
    In this episode, we cover:
    - **Architectural Implications of Agentic AI Workflows** (arXiv)
    - **On the Limits of Machine-Learned Ranking for Modern Microarchitectural Policies** (arXiv)
    - **The key CPU architecture you've never heard of: RISC-V - Red Shark News** (google_arch)
    - **AMD Zen 6 CPU architecture may include new optimisations to tackle game stutter - kitguru.net** (google_arch)
    - **NextSilicon Productizes Arbel RISC-V Core Into 64-Core Enterprise Processor - Quantum Zeitgeist** (google_arch)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    16 min
  • LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension
    ## Episode Summary
    In this episode, we cover:
    - **LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension** (arXiv)
    - **A Time-Multiplexed Spiking Neural Network Accelerator with Pipelined Readout for FPGA Inference** (arXiv)
    - **RISC-V vs ARM: Which Instruction Set Architecture Will Dominate the Future? - Electropages** (google_arch)
    - **Performance aware shared memory hierarchy model for multicore processors - Nature** (google_arch)
    - **Bit-Brick K1: Raspberry Pi 5 alternative with different CPU architecture, M.2 and PCIe support launches - Notebookcheck** (google_arch)
    ---
    *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
    15 min

About Condor Currents

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Condor Currents delivers concise breakdowns of the latest computer architecture research and RISC-V developments. Each episode covers recent arXiv papers on data prefetching, branch prediction, and…