Want a candid look at how women build durable careers in one of the world’s toughest industries? We sit down with three semiconductor leaders - Nitza Bosoco, Anne Meixner and Julia Freer - who share how early encouragement, gritty problem solving, and clear communication turned curiosity into impact. From summer jobs at national labs and early days at IBM to leading operations, test, and sustainability initiatives, their stories show why diverse voices aren’t just nice to have—they’re a competitive advantage.

We dig into the real moments: being the only woman in a test engineering group, pushing for inclusive language that actually changes culture, and navigating career pivots to balance family, flexibility, and ambition. You’ll hear how mentorship and sponsorship differ—and why you need both—plus specific tactics to make them work inside fast-moving chip companies. One unforgettable segment starts with a five-minute crash-and-burn presentation and becomes a two-year, teamwide communication overhaul that turns shy engineers into confident presenters ready for conferences and boardrooms.

Across materials science, advanced packaging, test and inspection, and sustainability, the thread is clear: communication is a core engineering skill. Writing reflective status reports, designing slides for decisions, and telling a tight technical story can accelerate yield improvements, align manufacturing and supply chain, and win executive support. We also tackle today’s DEI headwinds with a practical lens—keep the pipeline alive, promote from within, and build programs that outlast policy shifts. The conversation closes with why their new book matters: ordinary, relatable role models who show many valid paths into STEM and semiconductors.

Learn more about the book, Empowering Women in STEM. 

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Power electronics are quietly rewriting the rules of energy use—from the range of your EV to the efficiency of a hyperscale data center. Françoise sits down with Henkel’s Ram Trichur to unpack what’s driving the $67.5B surge in power semiconductors and why the move to wide bandgap materials like silicon carbide and gallium nitride is such a big deal. 

We break down the real differences between logic and power devices, then dive into where innovation is happening right now: die attach materials, thermal pathways, and manufacturing processes that can keep up with higher power densities. Ram explains why traditional wirebond packaging remains dominant in power, even as modules climb from 400 V to 800 V and beyond. You’ll learn how the industry is moving from solder to silver sintering for performance, and why copper-based sintering may be the breakthrough that balances cost, reliability, and manufacturability.

From discrete devices to full power modules, we explore the challenges of thinner die, copper leadframes, backside metallization compatibility, and bond line control. Ram shares Henkel’s roadmap for pressure-assisted copper sintering at lower temperatures and pressures in nitrogen, the multi-year qualification path customers expect, and how early sampling shortens time to scale. If you care about EV range, charger efficiency, industrial uptime, or greener data centers, this conversation connects the dots between materials science, packaging engineering, and system-level performance.

If you enjoyed this deep dive, follow the show, share it with a colleague who cares about SiC and GaN, and leave a quick review to help others find us. Got a question or a hot take on copper vs. silver sintering? Drop us a note and join the conversation.

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The floor in Phoenix was packed, and so were the ideas. We sat down with innovators across the stack—equipment makers, metrology experts, logistics strategists, and software leaders—to map the real state of advanced packaging and what it takes to build, measure, move, and power tomorrow’s chips.

EV Group kicked things off with a candid look at die-to-wafer realities: activation on film frame, then 100% overlay metrology that measures tens of thousands of points per hour so every die and corner is verified. They also unveiled LithoScale XT, a fully digital, maskless lithography system printing 300 mm at 60 wph—perfect for massive AI dies and fast design turns. 

Lab14 widened the frame with a portfolio approach: direct-write lithography, single-wafer processing, data prep, and analysis tools working as a coordinated line, with data sharing and AI feedback baked in.

Resilience and regionalization came to life through Kuehne+Nagel’s on-the-ground view: supplier clustering near fabs, cross-border trucking, time-critical services, and 4PL integration that gives real-time visibility and smarter capacity planning. 

ERS showed where throughput meets cost: photothermal debonding with lower stress and reusable glass carriers, demo centers in Taiwan (and planned in North America), plus surge demand for warpage repair as volumes rise.

Process control is moving into packaging with front-end rigor. Nova detailed metrology for hybrid bonding, chemistry monitoring of plating baths, X-ray and XPS/SIMS material insights, and the handling know-how to measure framed wafers and panels reliably. 

Nordson Test & Inspection highlighted AI-driven inspection, ultra-fast acoustic scanning, automated X-ray metrology, and sensor wafers that cut tool downtime and sharpen process windows. Comet showcased its CT and CA20 upgrades for 3D IC and TSV analysis.

Power dominated the later conversations. Siemens argued we need to design for energy from the chip through the blade, rack, and data center, simulating real workloads and cooling to slash gigawatts—then extend that thinking into the fab, where optimizing chillers and facilities already saves serious money. 

Onto Innovation brought it home with execution: the PACE Center now hosts partners’ tools, accelerating experiments for glass, TGV, and panel processes without waiting on public funds.

If you care about hybrid bonding, maskless lithography, CT for 3D ICs, panel-scale packaging, or cutting AI’s energy bill, this one is dense with takeaways and hard truths. Subscribe, share with a colleague who lives in the fab or data center, and leave a review telling us which insight you’ll act on first.

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A nationwide talent engine for chips is taking shape—and it’s built to scale. Recorded live at SEMICON West in Phoenix, we sit down with SEMI Foundation leaders to unpack the National Network for Microelectronics Education, a hub-and-node model designed to align schools, employers, and workforce systems. Backed by CHIPS Act funding through the National Science Foundation, NNME will fund multi-state regional nodes that modernize curricula, streamline upskilling, and share proven playbooks across the country. We also unveil the refreshed Chip Path portal, which maps your skills and interests to real jobs in fabs, equipment, and materials, and we highlight SEMI-Quest, a hands-on STEM experience designed to spark early curiosity about microelectronics.

Then we turn to sustainability where momentum is accelerating. The Semiconductor Climate Consortium has grown past 100 members and is shifting from baselines to projects that deliver measurable impact. We explore how the Energy Collaborative pushes for policy that opens affordable renewable power, while SCC advances user-side strategies—better emissions accounting, renewable procurement models, and fab energy efficiency. A core challenge emerges: hyperscalers often target net zero by 2030, while many chipmakers point to 2050. We dig into how coordinated innovation, shared standards, and advocacy can close that 20-year gap.

AI’s energy appetite raises the stakes, so we tackle both sides of the equation: adding clean capacity where it matters most and designing for lower power at the chip and fab level. From global cooperation across APAC, EU, and the U.S. to practical ways individuals and companies can act now, the throughline is collaboration with urgency. Ready to find your role in the future of chips—whether building skills, hiring smarter, or decarbonizing faster? Subscribe, share this episode with your team, and leave a review to help more people find these insights.

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We recorded live at IMAPS with Siemens, ACM Research, Shellback Semiconductor, DECA, Nordson Electronic Solutions, and VIEW Micro Metrology to explore how AI demand, chiplets, and panels are reshaping advanced packaging. We dig into 3D BLOX, thermal and test roadblocks, green chemistries, metrology at scale, and why the back end now leads innovation. Listen to learn about:

• The Siemens–ASE collaboration on 3D BLOX models and VIPACK workflows
• Interoperable YAML-based packaging definitions moving toward IEEE standard
• 3D stacking to cut picojoules per bit amid thermal and test limits
• Panel-level packaging economics, sizes, and lack of standards
• ACM Research updates in copper plating, bevel clean, frame clean, and compound deplating
• Batch spray versus single wafer trade-offs at Shellback Semiconductor
• HydrOzone green strip replacing legacy NMP in select flows
•The  DECA–SST deal for NVM chiplet package and SoC disaggregation
• Nordson Electronic Solutions' panel strategy, IntelliJet 1.1, Vantage platform, and warpage control
• VIEW Micro Metrology's high-throughput telecentric metrology across wafers and large panels

Learn more at imaps.org

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We record live at IMAPS to follow a first-time attendee’s leap into advanced packaging and a trio of high school students discovering semiconductors, robotics, and career paths that bridge disciplines. Along the way, we unpack speed-to-market, standards, hybrid vs TCB, and why AI skills matter.

• why a self-funded first conference can reset a career
• key takeaways from PDCs and technical talks
• time-to-market pressure across packaging workflows
• standards tension between front-end and packaging
• hybrid bonding promise versus TCB workhorse reality
• how to network with intent and follow through
• volunteering with IMAPS to build early-career hubs
• robotics as an on-ramp to semiconductors
• interdisciplinary routes into microelectronics
• student goals, mentors, and university paths
• practical questions to ask on the expo floor

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We sit down with Dr. Subu Iyer of UCLA to unpack chiplets vs dielets, why a universal ecosystem is missing, and how sub‑10 µm bump pitch could make protocols optional. Then we host a panel featuring John Knickerbocker, IBM; Mike Kelly, Amkor; and Tolga Tekin, Fraunhofer IZM on co‑packaged optics, bandwidth, and power for AI data centers.

• chiplet as design construct, dielet as physical die
• lack of universal chiplet ecosystem and interoperability
• bump pitch scaling and protocol overhead trade‑offs
• packaging purpose reframed as power, communication, and cooling
• economic shift and value capture in advanced packaging
• national competitiveness, prototyping access, and talent pipeline
• co‑packaged optics definition, drivers, and cost targets
• copper reach limits, latency, and bandwidth density for AI
• hyperscalers as early adopters and five‑year outlook

Learn more at imaps.org

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A semiconductor wafer travels around the globe five times on average before becoming the chip in your smartphone. Each journey represents a potential risk to device reliability that few consumers—or even industry professionals—ever consider.

Behind every high-performing semiconductor device lies a carefully orchestrated logistics operation ensuring these sensitive components arrive intact and functioning. As Francoise von Trapp discovers in this eye-opening conversation with John Desmond and Valentina Aplenalp of Kuehne+Nagel, the journey matters just as much as the manufacturing.

Drawing from his background in semiconductor design and manufacturing, John explains how vibration, temperature fluctuations, humidity, and even light exposure can compromise device integrity during transit. Wafers transported in specialized containers called FOUPs, delicate packaging materials, and critical replacement parts for manufacturing equipment all require extraordinary care throughout their global journeys.

Valentina reveals the sophisticated systems developed to protect these valuable shipments: real-time environmental monitoring sensors connected to 24/7 control towers, specialized air-ride vehicles, and climate-controlled packaging solutions. When emergencies arise—like a critical equipment failure threatening production—their time-critical logistics teams deliver replacement parts within hours, not days.

Most fascinating is the human element. The Semicon Chain certification program ensures every person who might handle semiconductor shipments receives specialized training, creating an end-to-end system where nothing is left to chance. As John puts it, they aim to be "the best partner that you never know you had"—the hidden force ensuring semiconductor reliability.

Whether you're a semiconductor professional, supply chain specialist, or simply curious about the invisible infrastructure supporting our digital world, this episode offers rare insight into how logistics enables technological innovation. 

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SEMI's flagship event, SEMICON West, is moving to Phoenix, Arizona this October 7-9, 2025, after 35 years in San Francisco, coinciding with the region's semiconductor manufacturing boom and $200 billion in announced investments. In this episode, Françoise speaks with SEMI Americas president, Joe Stockunas, who shares reasons for the move and what attendees can expect to experience. This includes: 

• Move driven by need to refresh the event and bring it closer to industry growth
• New October timing based on attendee feedback to avoid disrupting July holidays
• CEO Summit featuring keynotes from Arizona Governor Hobbs, TSMC, NVIDIA, and Intel
• Exhibition floor expanding to over 1,500 booths (50% increase from last year)
• Technical tracks focused on advanced packaging, AI, cybersecurity, and workforce development
• Street fair networking event Tuesday evening on 3rd Street
• Student attendance expected to jump from 700 to 7,000 thanks to proximity to Arizona's educational institutions
• Special SemiQuest exhibit at Arizona Science Museum running September through year-end
• Global Semicon events continue growing, with Semicon India doubling to 1,000 booths

For registration and complete program information, visit semiconwest.org or download the event app to navigate the show and build your agenda.

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The IMAPS International Symposium returns to the Town & Country Resort in San Diego from September 29-October 2, 2024, featuring restructured technical tracks, new Monday panel discussions, and exciting networking events including a special reception aboard the USS Midway aircraft carrier. General Chair Benson Chan and outgoing IMAPS President Erica Folk share what attendees can expect at this premier microelectronics packaging event.

• Expanded program with six focused technical tracks for better attendee experience
• New Monday afternoon panels on thermal challenges, HIR roadmap, and co-packaged optics
• Co-location with the new Thermal Management Conference (Wednesday-Friday)
• Special reception on the USS Midway aircraft carrier (requires RSVP during registration)
• Student engagement through high school tours, university booths, and the Posters & Pizza session
• Leadership transition as Erica Folk hands the presidency to Dan Kruger
• Multiple networking opportunities throughout the week including the Exhibitor Happy Hour
• Volunteer opportunities that provide valuable professional development and career connections

Register now at imaps.org to secure your spot at the symposium and don't forget to RSVP for the special Midway reception.

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