Five Minute VHDL Podcast

By Francesco Richichi

Let's talk about hardware design using VHDL... more

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FAQs about Five Minute VHDL Podcast:

How many episodes does Five Minute VHDL Podcast have?

The podcast currently has 33 episodes available.

Five Minute VHDL Podcast episodes:

March 06, 2019 Ep#16-VHDL process
And now is time to introduce formally a Process
link to the images

https://t.me/SurfVhdl/78

Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: [email protected]

Telegram:
https://t.me/francesco_surfvhdl

Teachable courses
https://surf-vhdl.link/courses

Music by Francis Preve - https://www.francispreve.com
...more
8min
March 01, 2019 Q&A#06- How can I generate a new clock from a reference clock?
I receiver a question from Sandip. He got my reference, from my post on DDS.

The question is:
“I want to generate Square of 999kHz, 1000kHz and 1001kHzin VHDL Language and that would be implemented on a Zynq ZC702 evaluation board.
Is it possible by using the DDS.? Can you provide your expertise and comment on it.”

Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: [email protected]

Telegram:
https://t.me/francesco_surfvhdl

Teachable courses
https://surf-vhdl.link/courses

Music by Francis Preve - https://www.francispreve.com
...more
11min
February 14, 2019 Ep#15-VHDL Packages
VHDL Packages

http://t.me/SurfVhdl/74

Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: [email protected]

Telegram:
https://t.me/francesco_surfvhdl

Teachable courses
https://surf-vhdl.link/courses

Music by Francis Preve - https://www.francispreve.com
...more
4min
February 11, 2019 Ep#14-VHDL object
After signal introduction, let's view what are the remaining VHDL objects

Images
https://t.me/SurfVhdl/72

Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: [email protected]

Telegram:
https://t.me/francesco_surfvhdl

Teachable courses
https://surf-vhdl.link/courses

Music by Francis Preve - https://www.francispreve.com
...more
7min
February 10, 2019 Q&A#05- Does the USB transfer work as UART?
I received a question from Haitham. He have to connect a computer to an FPGA using USB connection in order to transfer data from FPGA to the PC.
Haitham is following my VHDL course “Start Learning VHDL Using FPGA”. In this course the last LAB implement communication between PC and FPGA using UART channel.
After starting the course, Haitham asked me: “Does the USB transfer work as UART”?
Let’s see the answer. Here the link to the picture on the telegram channel

https://t.me/SurfVhdl/68

Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: [email protected]

Telegram:
https://t.me/francesco_surfvhdl

Teachable courses
https://surf-vhdl.link/courses

Music by Francis Preve - https://www.francispreve.com
...more
10min
February 08, 2019 QA#04-What is the VHDL design flow
In this Q&A episode I want to answer to the question on what is the VHLD design flow
To better follow the episode, see the picture on the telegram channel

https://t.me/SurfVhdl/65

Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: [email protected]

Telegram:
https://t.me/francesco_surfvhdl

Teachable courses
https://surf-vhdl.link/courses

Music by Francis Preve - https://www.francispreve.com
...more
8min
February 07, 2019 Ep#13-a way to remember-the flip-flop
Introducing Flip-Flop in VHDL

Link to the picture in the telegram channel

https://t.me/SurfVhdl/61

Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: [email protected]

Telegram:
https://t.me/francesco_surfvhdl

Teachable courses
https://surf-vhdl.link/courses

Music by Francis Preve - https://www.francispreve.com
...more
6min
February 05, 2019 QA#3-plzz send the test bench
This is the question many of you ask me very often
I wish to give you some hint and a test bench template I use in my VHDL designs

Here the link to the test bench template: https://t.me/SurfVhdl/58

Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: [email protected]

Telegram:
https://t.me/francesco_surfvhdl

Teachable courses
https://surf-vhdl.link/courses

Music by Francis Preve - https://www.francispreve.com
...more
4min
February 03, 2019 Ep#12-VHDL Simulation
A brief overview to setup a ModelSim simulation environment
Link to the episode#12 picture
t.me/SurfVhdl/53

Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: [email protected]

Telegram:
https://t.me/francesco_surfvhdl

Teachable courses
https://surf-vhdl.link/courses

Music by Francis Preve - https://www.francispreve.com
...more
6min
February 01, 2019 Ep#11-what is a signal
Introduce signal in VHDL, what is a signal and how to use it.

Image relative to this episode

Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: [email protected]

Telegram:
https://t.me/francesco_surfvhdl

Teachable courses
https://surf-vhdl.link/courses

Music by Francis Preve - https://www.francispreve.com
...more
4min

FAQs about Five Minute VHDL Podcast:

How many episodes does Five Minute VHDL Podcast have?

The podcast currently has 33 episodes available.