The Hardware Podcast with Fexingo: Chips, Devices, and Electronics Engineering Conversations

This episode explores the shift from research-lab silicon photonics to commercial foundry production. Lucas and Luna discuss how TSMC, Intel, and GlobalFoundries are integrating optical components alongside traditional CMOS, the role of the 300-millimeter wafer platform, and what this means for datacenter interconnect bandwidth. The conversation focuses on the practical engineering challenges—waveguide loss, laser integration, and thermal stability—and why the industry believes now is the moment to scale. Specific examples include the co-packaged optics roadmap at 800G and 1.6T Ethernet, and the emergence of multi-die optical interposers. No hype, just the physics and economics driving this manufacturing transition.

#SiliconPhotonics #ChipManufacturing #TSMC #Intel #GlobalFoundries #OpticalInterconnects #Datacenter #CoPackagedOptics #PhotonicsFoundry #300mmWafer #CMOS #Waveguide #LaserIntegration #Technology #Hardware #FexingoBusiness #BusinessPodcast #Semiconductors

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In this episode of The Hardware Podcast, Lucas and Luna dive into the emerging world of photonic computing cores. They explore how companies like Lightmatter and Ayar Labs are replacing traditional electronic interconnects with silicon photonics to move data at the speed of light. The discussion centers on a key milestone: Lightmatter's Envise chip, which integrates photonic cores for AI inference, achieving a 10x improvement in energy efficiency over purely electronic processors. Lucas breaks down the physics of how photonic cores use waveguides and modulators to encode data in light, avoiding the heat and bandwidth bottlenecks of copper traces. Luna questions the manufacturing challenges, from integrating photonic components with CMOS to the cost of laser sources. They also touch on the potential for optical computing to reshape data centers, reducing latency in hyperscale AI workloads. The episode balances technical depth with real-world applicability, ensuring listeners walk away understanding why photonic cores might be the next big shift in chip architecture.

#Photonics #SiliconPhotonics #OpticalComputing #Lightmatter #AyarLabs #AIAcceleration #ChipDesign #DataCenter #Interconnects #EnergyEfficiency #Waveguide #CMOSIntegration #Hardware #Technology #FexingoBusiness #BusinessPodcast #HardwarePodcast #ElectronicsEngineering

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In this episode of The Hardware Podcast with Fexingo, Lucas and Luna explore how chipmakers are turning to additive manufacturing — essentially 3D printing — to build the microscopic copper interconnects that connect transistors on a die. We focus on a specific breakthrough from a company called Applied Nanotools, which demonstrated a process called 'superconformal electrodeposition' that deposits copper in trenches just 10 nanometers wide without voids. Lucas explains why traditional subtractive etching hits a wall below 7 nanometers, and how printed interconnects could reduce resistance by 40 percent compared to conventional damascene processes. Luna asks whether this technique is production-ready or still a lab curiosity, and Lucas points to early adoption by a major memory manufacturer in 2025. We also touch on the implications for chip yield, power density, and the roadmap beyond 2-nanometer nodes. If this episode gives you a concrete insight you can share, listener support at buy me a coffee dot com slash fexingo keeps the show ad-free.

#AdditiveManufacturing #ChipInterconnects #AppliedNanotools #SuperconformalElectrodeposition #CopperPrinting #NanometerFabrication #SemiconductorManufacturing #3DPrintedChips #DamasceneProcess #ResistanceReduction #NodeScaling #MemoryManufacturing #ChipYield #PowerDensity #Technology #HardwarePodcast #FexingoBusiness #BusinessPodcast

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For decades, silicon has been the workhorse of chipmaking, but it's hitting a thermal wall. In this episode, Lucas and Luna explore why chip designers are now experimenting with diamond substrates — a material that conducts heat five times better than copper. They look at how companies like Akashic Systems and Stanford researchers are fabricating thin-film diamond layers directly on CMOS wafers, potentially lowering operating temperatures by 20°C. The hosts break down the cost challenge, the scalability question, and why this isn't just a lab curiosity: a startup just raised $40 million to commercialize diamond wafers for AI accelerators. If current roadmaps hold, the first commercial chips with embedded diamond layers could tape out as soon as 2028.

#DiamondSubstrates #ChipThermalManagement #SemiconductorMaterials #AkashicSystems #StanfordEngineering #CMOS #AIChips #ThermalConductivity #WaferFabrication #ChipDesign #Technology #FexingoBusiness #BusinessPodcast #HardwarePodcast #ChipsAndDevices #SemiconductorInnovation #DataCenterCooling #MaterialScience

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Lucas and Luna explore the race to put high-speed optical modems directly on silicon chips, moving data with light instead of electricity. They examine the bottleneck at the chip's edge, where electrical I/O can't keep up with internal compute speeds. The conversation focuses on a specific breakthrough: Intel's integrated hybrid silicon laser, announced in 2024, which combines an indium phosphide laser with a silicon photonics waveguide on the same die. They discuss how this shrinks transceiver costs from thousands of dollars to chip-scale, and why it matters for AI clusters, hyperscale data centers, and the future of bandwidth. Key numbers: current electrical SerDes at 112 Gbps per lane, optical links approaching 200 Gbps per lane, and the power savings of 3-5 pJ/bit for photonics versus 10-15 pJ/bit for electrical. The hosts also touch on the challenges of thermal stability and manufacturing yield.

#SiliconPhotonics #OpticalInterconnects #HybridSiliconLaser #ChipDesign #DataCenter #AIClusters #BandwidthBottleneck #Intel #IndiumPhosphide #IntegratedPhotonics #OpticalModem #SerDes #ElectronicsEngineering #Technology #FexingoBusiness #BusinessPodcast #HardwarePodcast #Chips

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On this episode of The Hardware Podcast, Lucas and Luna explore the quiet but crucial shift toward dedicated analog front-end (AFE) chips in modern electronics. With wireless sensor nodes expected to reach 75 billion by 2030, designers are separating analog conditioning from digital processing to cut noise and save power. Lucas breaks down how ADI's AD5941 bio-impedance AFE is being used in wearable health patches, and why the move from integrated ADC to standalone AFEs echoes the earlier transition from general-purpose MCUs to dedicated sensor hubs. The hosts also discuss the challenge of designing AFEs for edge AI—where precision analog must coexist with neural network inference—and why companies like STMicroelectronics and Texas Instruments are investing heavily in configurable AFE architectures. Whether you're an embedded engineer or just curious about how your smartwatch measures stress, this episode explains the chip inside the sensor.

#AnalogFrontEnd #ChipDesign #Semiconductors #WearableTech #EdgeComputing #SensorTechnology #ADI #STMicroelectronics #TexasInstruments #BioImpedance #SignalConditioning #MixedSignal #LowPowerDesign #HealthTech #IoT #HardwareEngineering #FexingoBusiness #BusinessPodcast

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Episode 67 of The Hardware Podcast explores why chip designers are turning to embedded optical interconnects to solve data movement bottlenecks. Lucas and Luna unpack the physics limits of copper wiring, the 'optical transceiver in package' approach pioneered by companies like Ayar Labs and Intel, and what it means for performance and power. They discuss the recent prototype from a major foundry showing a 10x bandwidth density improvement over electrical interconnects, and the manufacturing challenges of integrating photonics into standard CMOS processes. Tune in for a concrete look at the technology that could reshape chip-to-chip communication in AI and HPC clusters.

#EmbeddedOpticalInterconnects #SiliconPhotonics #AyarLabs #Intel #ChipDesign #DataMovement #BandwidthDensity #CMOSIntegration #AIHardware #HPC #OpticalTransceiver #CopperInterconnects #Semiconductors #Technology #FexingoBusiness #BusinessPodcast #TheHardwarePodcast #Fexingo

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Episode 66 of The Hardware Podcast. Lucas and Luna explore glass substrates for chip packaging — a material shift that could reshape how processors handle bandwidth, heat, and interconnect density. They discuss why Intel and Samsung are investing in glass core substrates, the manufacturing challenges at scale, and how this technology could enable faster AI accelerators and data-center chips. Specific numbers: glass substrates can reduce signal loss by 30% compared to organic materials and support 50% finer line widths. The hosts explain why glass is suddenly viable after decades of being dismissed as too brittle, and what it means for the next generation of heterogeneous integration. No hype — just the engineering reality.

#GlassSubstrates #ChipPackaging #Semiconductor #Intel #Samsung #AdvancedPackaging #HeterogeneousIntegration #AIAccelerators #DataCenter #MaterialScience #Corning #Technology #HardwarePodcast #FexingoBusiness #BusinessPodcast #ElectronicsEngineering #ChipDesign #Manufacturing

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In this episode of The Hardware Podcast, Lucas and Luna explore how advanced chip designers are tackling electromigration — the slow migration of metal atoms that can cause chip failure — at the three-nanometer node. They dive into the physics behind copper interconnects, why cobalt and ruthenium are replacing copper in critical layers, and how TSMC and Intel are using barrier engineering and novel liner materials to extend chip lifespan. Specific data includes the 10x improvement in electromigration resistance achieved with cobalt liners at 2nm dimensions. The discussion also touches on the hidden role of grain boundaries and the trade-off between performance and reliability. A must-listen for anyone curious about the unsung materials science behind modern processors.

#Electromigration #Semiconductors #ChipDesign #3Nanometer #TSMC #Intel #CopperInterconnects #Cobalt #Ruthenium #MaterialsScience #Reliability #Technology #Hardware #Engineering #FexingoBusiness #BusinessPodcast #TheHardwarePodcast #Podcast

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Episode 64 of The Hardware Podcast explores how chip designers are embedding dedicated hardware firewalls directly into networking silicon to protect data in motion. Lucas and Luna break down the architecture behind in-line security engines that inspect packets at line rate without sacrificing throughput. They discuss a real deployment at a major cloud provider that cut latency by 40 percent compared to software-based filtering, and walk through the trade-offs of putting firewall logic on the data plane versus the control plane. The conversation also touches on the rise of programmable match-action pipelines and why hyperscalers are pushing for open-source P4-based designs. If you design network chips or care about how your cloud traffic stays safe, this episode gives you the technical details that matter.

#HardwareFirewall #DataPlaneSecurity #NetworkChips #P4Programming #InLineEncryption #CloudSecurity #MatchActionPipeline #LineRateInspection #LatencyReduction #HyperscalerNetworking #ChipDesign #HardwareSecurity #Technology #HardwareEngineering #FexingoBusiness #BusinessPodcast #SiliconInnovation #NetworkProcessor

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