The Hardware Podcast with Fexingo: Chips, Devices, and Electronics Engineering Conversations

On today's Hardware Podcast, Lucas and Luna explore heterogeneous integration — the chip design strategy that stacks silicon, III-V compounds, and photonics into a single package. They break down how this approach enabled AMD's MI300X AI accelerator, which combines nine chiplets on a single interposer to rival NVIDIA's flagship GPU. The hosts discuss the technical challenges of mixing different process nodes, the role of TSMC's CoWoS-L packaging, and why heterogeneous integration is becoming essential as Moore's Law slows. Listeners will learn how this technique cuts costs, improves performance, and why every major chipmaker is racing to adopt it.

#HeterogeneousIntegration #AMD #MI300X #Chiplets #AdvancedPackaging #TSMC #CoWoS #MooresLaw #AIChips #Semiconductors #GPU #NVIDIA #III-V #SiliconPhotonics #Technology #Hardware #FexingoBusiness #BusinessPodcast

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Episode 52 of The Hardware Podcast dives into the hidden grid inside every chip: the power delivery network, or PDN. Lucas and Luna explore why traditional on-chip power grids are hitting a wall as transistors shrink below 3 nanometers, and how the industry is turning to a radical alternative called 'buried power rails.' Anchored by a real-world example from a recent IEEE paper on Intel's 18A process, they explain how moving power wires to the back of the chip frees up space for data signals and cuts voltage droop by 15 percent. The conversation covers the manufacturing challenges of building trenches in silicon, the trade-off between resistance and capacitance, and why this shift could reshape chip design for the next decade. If you've ever wondered how your smartphone's processor stays stable under full load—or why future chips might look completely different under a microscope—this episode gives you the concrete engineering story behind the transition.

#PowerDeliveryNetwork #BuriedPowerRails #ChipDesign #Semiconductors #Intel18A #VoltageDroop #IRDrop #BacksidePowerDelivery #NanometerTransistors #IEESSC #ChipArchitecture #HardwareEngineering #Technology #ElectronicsEngineering #FexingoBusiness #BusinessPodcast #TechPodcast #TheHardwarePodcast

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Episode 51 of The Hardware Podcast explores the emerging field of runtime-reconfigurable logic. Lucas and Luna dive into how a startup called FlexLogix is embedding reconfigurable data-path units inside server chips, allowing the chip to rewire its own circuits while the system is running—no new silicon needed. The discussion centers on a real deployment at a major cloud provider where reconfigurable logic cut a critical inference latency by 40 percent without any hardware swap. The hosts explain the difference between traditional FPGA-based reconfiguration and these new on-die tiles, the trade-offs in area and power, and why every hyperscaler is now funding internal research groups on this exact idea. If today's conversation gave you something useful, the show stays ad-free thanks to listener support at buy me a coffee dot com slash fexingo.

#ReconfigurableComputing #FlexLogix #RuntimeReconfiguration #ChipDesign #FPGA #DataPath #HardwareAcceleration #CloudComputing #Semiconductors #Inference #Latency #Technology #FexingoBusiness #BusinessPodcast #HardwarePodcast #ElectronicsEngineering #Chips #Devices

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Episode 50 of The Hardware Podcast dives into the rising trend of on-chip security cores — dedicated hardware engines that handle encryption, attestation, and key management separately from the main CPU. Lucas and Luna explore why Apple's Secure Enclave, Google's Titan M, and AMD's Platform Security Processor signal a fundamental shift in chip design. They unpack the numbers: a modern server chip can spend up to 10% of its transistor budget on security logic, and how that trade-off changes performance and power. Plus, a look at the open-source OpenTitan project and what it means for the future of trusted computing. If this conversation gave you something usable, the show runs on listener support.

#SecurityCoProcessor #HardwareSecurity #SecureEnclave #TitanM #OpenTitan #ChipDesign #HardwareEngineering #TrustedComputing #AppleSilicon #AMD #Google #RootOfTrust #EncryptionHardware #Semiconductor #Technology #FexingoBusiness #BusinessPodcast #HardwarePodcast

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Lucas and Luna dive into the unsung hero of chip performance: the substrate. They explore how Intel's glass substrate breakthrough is reshaping the race for faster, cooler, and more efficient processors. With real-world examples like AMD's EPYC and NVIDIA's GB200, they unpack the materials science, supply chain implications, and why the substrate might be the next frontier in Moore's Law.

#ChipSubstrates #GlassSubstrates #Intel #AMD #NVIDIA #Semiconductors #Moore'sLaw #MaterialsScience #AdvancedPackaging #GB200 #EPYC #Technology #HardwareEngineering #FexingoBusiness #BusinessPodcast #TechPodcast #ChipDesign #SupplyChain

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Episode 48 dives into the growing complexity of simulating multi-die chip designs, where chiplets and advanced packaging create new verification challenges. Lucas and Luna explore how EDA tools are evolving to handle system-level thermal, power, and signal integrity issues that single-die designs never faced. With specific data on simulation time blow-ups and real examples from the latest design flows, they examine why multi-die simulation is becoming a bottleneck—and the techniques engineers are using to break through. A must-hear for anyone following the shift to heterogeneous integration.

#ChipDesign #MultiDie #Simulation #EDA #AdvancedPackaging #Chiplets #SignalIntegrity #ThermalManagement #PowerIntegrity #Verification #HeterogeneousIntegration #Semiconductor #Technology #HardwarePodcast #FexingoBusiness #BusinessPodcast #ElectronicsEngineering #DesignTools

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Episode 47 of The Hardware Podcast digs into the quiet shift happening inside chip fabrication lines: carbon nanotube interconnects. Lucas and Luna discuss why copper interconnects are hitting fundamental limits at the 2-nanometer node, how carbon nanotubes can carry more current with less resistance, and what TSMC and IBM have disclosed about their early research. They walk through a specific 2025 paper from the IEEE International Electron Devices Meeting that showed a nanotube-based test structure delivering 30 percent lower latency than copper at equivalent line widths. The episode also covers the manufacturing hurdles — alignment, density, contact resistance — and why this isn't a near-term replacement but a plausible mid-decade transition. Concrete, engineering-focused, and grounded in real data.

#CarbonNanotubeInterconnects #ChipDesign #SemiconductorEngineering #TSMC #IBM #CopperLimits #2nmNode #IEDM #InterconnectScaling #Nanoelectronics #HardwarePodcast #Technology #ChipManufacturing #FexingoBusiness #BusinessPodcast #MaterialsScience #AdvancedPackaging #ResistanceCapacitance

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As memory bandwidth becomes the bottleneck for high-performance computing, chip designers are moving DRAM from the motherboard into the same package as the processor. This episode explains the technology behind high-bandwidth memory (HBM), how it stacks memory dies vertically with through-silicon vias, and why it challenges traditional DDR. Lucas and Luna break down the specific engineering trade-offs: why HBM delivers ten times the bandwidth per watt of conventional memory, but at a steep cost in manufacturing complexity and yield. They look at how HBM stacks are built, how they connect to a processor via an interposer, and why companies like AMD, NVIDIA, and Intel are betting big on this approach. The conversation also touches on the dark side: thermal management in a 3D stack, the challenge of testing each layer before assembly, and why HBM remains too expensive for mainstream PCs. Listeners will walk away understanding exactly why your next smartphone or laptop might not have sockets for RAM anymore.

#HBM #HighBandwidthMemory #DRAM #ChipDesign #Semiconductor #MemoryBandwidth #AdvancedPackaging #ThroughSiliconVia #TSV #Interposer #AMD #NVIDIA #Intel #Chiplet #Technology #SemiconductorIndustry #FexingoBusiness #BusinessPodcast

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Episode 45: Lucas and Luna explore the emerging field of silicon photonics—using light instead of electricity to move data inside chips. They break down a real-world case: a startup called Ayar Labs has demonstrated an optical I/O chiplet that transfers data at 4 terabits per second while cutting power consumption by 80 percent compared to traditional copper interconnects. The hosts explain how this technology sidesteps the bandwidth bottleneck that has plagued chip-to-chip communication for years, why Intel and AMD are investing heavily, and when we might see photonics in consumer devices. No hype, just the engineering trade-offs that matter.

#SiliconPhotonics #OpticalI/O #ChipDesign #AyarLabs #Intel #AMD #BandwidthBottleneck #DataCenter #Technology #Semiconductor #Photonics #Chiplet #Interconnect #FiberOptic #Laser #Modulator #FexingoBusiness #BusinessPodcast

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Episode 44 of The Hardware Podcast dives into the quiet but transformative shift happening inside chip packaging labs: the move from organic laminates to glass substrates. Lucas unpacks the physics—why glass offers better dimensional stability, lower signal loss, and the ability to pack more chiplets in a single package. Luna brings a concrete example: Intel's 2025 announcement of a glass-substrate test vehicle for high-performance computing, and asks whether the material can scale beyond niche use. The hosts walk through the manufacturing hurdles—drilling micron-scale vias through glass without cracking it—and the supply-chain implications for substrate suppliers like Ibiden and Unimicron. By the end, you'll understand why the chip industry is suddenly excited about a material that's been around for millennia.

#GlassSubstrate #ChipPackaging #Semiconductor #AdvancedPackaging #Intel #Ibiden #Unimicron #Chiplets #SubstrateTechnology #MooreLaw #HighPerformanceComputing #ThermalManagement #SignalIntegrity #ChipManufacturing #ElectronicsEngineering #Hardware #Technology #FexingoBusiness

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