The Hardware Podcast with Fexingo: Chips, Devices, and Electronics Engineering Conversations

Episode 43 of The Hardware Podcast dives into the open-source RISC-V instruction set architecture, which is gaining traction from tiny IoT controllers to server-class processors. Lucas and Luna break down why companies like NVIDIA, Alibaba, and the Chinese government are betting on RISC-V, how it challenges Arm's licensing model, and what a $1.5 billion venture investment means for the future of chip design. They walk through a concrete example: Alibaba's Xuantie 910 CPU core, which powers smart speakers and edge servers in China. The hosts explain how RISC-V lets firms customize instructions for AI workloads without paying Arm's royalties. They also discuss the fragmentation risk and why some analysts say RISC-V could capture 25% of the core market by 2030. If you've ever wondered whether open-source hardware can truly compete with proprietary giants, this episode gives you the numbers and the context.

#RISC-V #OpenSourceHardware #InstructionSetArchitecture #ChipDesign #Semiconductors #ArmAlternatives #NVIDIA #Alibaba #Xuantie910 #AIAcceleration #CustomCores #VentureCapital #Technology #HardwarePodcast #FexingoBusiness #BusinessPodcast #ChipsAndDevices #ElectronicsEngineering

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Episode 42 of The Hardware Podcast dives into a material most people have never heard of but is absolutely critical to every chip ever made: photoresist. Lucas and Luna explore why a single gallon of the high-end photoresist used in extreme ultraviolet lithography can cost over $2,000 — more than gold by weight. They break down the chemistry, the purity requirements that make it so expensive, and the handful of Japanese and German companies that dominate the supply. This episode also touches on the geopolitical stakes, as Taiwan and the US scramble to build domestic photoresist production. If you've ever wondered what liquid actually turns into the circuits on a chip, this is the episode.

#Photoresist #EUVLithography #ChipManufacturing #SemiconductorSupplyChain #TokyoOhka #JSR #SumitomoChemical #Fujifilm #ChemicallyAmplifiedResist #Methanol #IntegratedCircuits #ChipFab #TSMC #ASML #Technology #Hardware #FexingoBusiness #BusinessPodcast

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Every chip that ends up in a smartphone, car, or data center passes through a single high-stakes checkpoint called final test. This episode goes inside the multi-million-dollar test floor at a typical OSAT facility — think Amkor or ASE — where handlers sort good dies from bad at speeds of tens of thousands per hour. We look at how the industry is coping with the explosion of test time as chips get more complex, why some companies are moving test in-house, and how a technique called 'system-level test' is catching escapes that traditional methods miss. Lucas and Luna also discuss the economics: test can account for 10 to 30 percent of a chip's total cost, and that share is rising fast. If you've ever wondered how a chip goes from a wafer to a finished product with a guarantee that it works, this is the back-end story that doesn't get told.

#FinalTest #ChipTesting #OSAT #Semiconductor #SemiconductorManufacturing #SystemLevelTest #ATE #Amkor #ASE #TestCost #ChipProduction #ElectronicsEngineering #Technology #HardwarePodcast #Chips #FexingoBusiness #BusinessPodcast #ChipEconomics

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Chip defects cost the semiconductor industry billions every year. But a quiet revolution in built-in self-test circuitry is changing the economics of reliability. Lucas explains how chips can now run their own health checks, diagnose faults, and even reconfigure around broken cores — all without external test equipment. Luna pushes back on whether this adds too much complexity. Using examples from modern server processors and automotive microcontrollers, this episode reveals the design trade-offs behind chips that never stop testing themselves. If today's hardware conversation gave you something useful, listener support keeps it ad-free at buy me a coffee dot com slash fexingo.

#BuiltInSelfTest #ChipReliability #SemiconductorDesign #FaultTolerance #ChipDefects #YieldImprovement #SelfHealingChips #EmbeddedTesting #AutomotiveChips #ServerProcessors #DesignForTest #Technology #HardwareEngineering #FexingoBusiness #BusinessPodcast #TechPodcast #ChipDesign #ElectronicsEngineering

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Semiconductor manufacturing gets all the glory for extreme ultraviolet lithography and nanometer-scale transistors, but there is a less glamorous step that happens dozens of times per chip: the photomask. In this episode, Lucas and Luna explore how photomasks act as the precision stencils that define every circuit layer, why a single defect smaller than a virus can ruin an entire batch, and how the mask-making industry is racing to keep up with ever-shrinking process nodes. They discuss the economics of mask shops, the shift from binary to curvilinear masks, and the quiet pressure that mask alignment places on chip yield. This is the behind-the-scenes story of the tool that makes every chip possible — and the unsung engineering that keeps Moore's Law on track.

#Photomask #ChipManufacturing #Lithography #Semiconductor #Moore'sLaw #MaskAlignment #EUV #Yield #Sub3nm #CurvilinearMask #OpticalProximityCorrection #Technology #Hardware #Engineering #FexingoBusiness #BusinessPodcast #Chips #Devices

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In this episode of The Hardware Podcast, Lucas and Luna dive into the engineering marvel behind extreme ultraviolet lithography—the machines that print the world's tiniest transistors. They explain why EUV light is generated by vaporizing tiny droplets of tin with a laser, how mirrors replace lenses because UV light can't travel through glass, and the staggering precision required to align layers within a single nanometer. Lucas breaks down the monopoly of ASML, the Dutch company that builds every EUV system, and why each machine costs over $150 million. Luna brings a practical example: how a modern smartphone chip's 3-nanometer process relies on 30 to 80 EUV layers, each requiring a vacuum chamber the size of a bus. They discuss the physics of reflective optics, the challenge of plasma stability, and why this technology is the bottleneck for Moore's Law. A must-listen for anyone curious about the physical limits of computing.

#EUV #Lithography #ASML #ChipManufacturing #Nanometer #Photonics #PlasmaPhysics #Semiconductor #MooreLaw #Transistor #Technology #Hardware #Engineering #FexingoBusiness #BusinessPodcast #TechPodcast #DeepTech #PhotonLithography

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Episode 37 of The Hardware Podcast dives into the chiplet revolution — why major chipmakers are moving away from monolithic dies and stitching together smaller silicon tiles instead. Lucas explains how AMD's Zen architecture proved the model with its Zen 2 chiplet design, using four compute dies plus an I/O die on a single package. Luna questions the cost and complexity trade-offs, from interconnect standards like Universal Chiplet Interconnect Express (UCIe) to yield improvements and thermal challenges. They discuss how Intel, AMD, and emerging startups are adopting chiplets for everything from data center CPUs to AI accelerators, and what this shift means for the future of Moore's Law. A concrete look at why splitting chips apart is the smartest way to keep making them faster.

#Chiplets #Semiconductor #AMD #ZenArchitecture #ChipDesign #AdvancedPackaging #UCIe #Moore'sLaw #Technology #Hardware #DataCenter #AI #CPU #Yield #Interconnect #FexingoBusiness #BusinessPodcast #TheHardwarePodcast

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In Episode 36 of The Hardware Podcast, Lucas and Luna explore the quiet revolution in chip packaging that is extending Moore's Law. They explain how 2.5D and 3D packaging allow designers to combine chiplets from different process nodes, boosting performance without shrinking transistors. The hosts walk through a real example: how an AI accelerator uses interposers and hybrid bonding to stack memory directly on logic, slashing latency. They also touch on the role of TSMC's CoWoS and Intel's EMIB technologies, and why thermal management remains the biggest hurdle. Listeners will learn why packaging, not lithography, is now the frontier of chip innovation.

#AdvancedPackaging #ChipDesign #Semiconductor #Moore'sLaw #Chiplets #2.5D #3DStacking #Interposer #HybridBonding #TSMC #CoWoS #Intel #EMIB #AIAccelerator #ThermalManagement #Technology #FexingoBusiness #BusinessPodcast

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Episode 35 of The Hardware Podcast with Fexingo dives into the quiet revolution happening inside chip design: the shift away from traditional SRAM toward new on-chip memory architectures like embedded DRAM and resistive RAM. Lucas and Luna explain why memory now consumes 40 to 60 percent of chip area in a typical processor, and why the old cache hierarchy is breaking down. They explore a concrete example—Apple's M-series Ultra chips, which use a massive 192 MB of on-chip memory—and walk through the tradeoffs between density, latency, and power. The conversation also covers the challenges of integrating new memory materials into standard CMOS processes, and why companies like Intel and TSMC are betting on different approaches. If you've ever wondered why chip performance gains have slowed even as transistor counts keep rising, this episode offers a clear, ground-level explanation.

#OnChipMemory #SRAM #EmbeddedDRAM #ResistiveRAM #RRAM #AppleSilicon #M3Ultra #Intel #TSMC #ChipDesign #MemoryWall #CacheHierarchy #Technology #Semiconductors #Hardware #HardwareEngineering #FexingoBusiness #BusinessPodcast

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In Episode 34, Lucas and Luna unpack a quiet revolution that rarely makes headlines: advanced chip packaging. While everyone obsesses over transistor shrinks, the way chips get physically assembled is becoming a bottleneck and an opportunity. Lucas explains why TSMC's CoWoS packaging is suddenly critical for AI accelerators, how Intel is betting on Foveros, and why the cost per extra millimeter of silicon interposer can run into millions. Luna asks whether the packaging renaissance means old fabs can stay relevant. They also explore how substrate shortages—yes, the board underneath—are delaying high-end chips for months. Specific examples: NVIDIA's H100 supply constraints, Apple's UltraFusion packaging for M-series, and the $3 billion Samsung is investing in panel-level packaging. A clear look at the layer of hardware engineering most people overlook.

#ChipPackaging #AdvancedPackaging #TSMC #CoWoS #IntelFoveros #SamsungPackaging #NVIDIAH100 #AppleUltraFusion #Semiconductor #ChipManufacturing #SubstrateShortage #AIHardware #HardwareEngineering #Technology #FexingoBusiness #BusinessPodcast #TheHardwarePodcast #ElectronicsEngineering

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