Zero to ASIC Course

https://wiki.f-si.org/index.php/FSiC2022

00:00 Intro

01:04 Charles Papon

05:18 Tristan Gingold

09:10 Staf Verhaegen

11:30 Naohiko Shimizu

16:38 Tim Edwards

20:46 Harald Pretl

21:40 Mirjana Videnovic-Misic

00:00 Intro

03:05 Teo's work on optimising adders

04:35 Proppy's work with Jupyter notebooks

05:32 Open source is the key to innovation

07:51 GF180

08:10 When teaching the design of standard cell libraries, what do students struggle most with?

10:15 What does he think engineers least understand, but should, about standard cells?

12:14 What is your tool flow?

16:00 How many cells do you need in a library?

19:24 Why do we need another cell library for GF180?

20:40 How far are we in terms of opensource tools from commercial tools?

22:20 Liberate

25:20 Does he think automated layout of standard cells will be competitive with hand layout in nanometer processes?

29:21 Are there any circuit families from the past that deserve new attention with Moore's Law slowing down?

33:10 Any theories on why nVidia would make a 7.5T standard cell library?

Contact James here: [email protected] or on twitter: https://twitter.com/JamesStineJr

Teo's adders: https://github.com/mattvenn/instrumented_adder

MPW6 walkthrough: https://youtu.be/MNuoYz_MM-c

https://developers.google.com/silicon

Free silicon conference: https://wiki.f-si.org/index.php/FSiC2022

Newsletter: https://www.zerotoasiccourse.com/newsletter/

00:00 intro

00:13 moving pictures

00:29 Proppy put sky130 into google colab notebooks: https://colab.research.google.com/gist/proppy/964fa4b9277c3baf9e731872bbad93e4/zerotoasic_project1_1.ipynb#scrollTo=TGgki8I-wPWa

01:12 Teo's work on optimising adders https://blog.yosyshq.com/p/optimising-adders/

01:53 MPW6 reminder

02:20 Level up your RTL call https://twitter.com/matthewvenn/status/1514927352010186754

02:46 $100 tapeout

04:26 Chips Alliance event https://chipsspring2022.sched.com/

04:42 WOSET https://twitter.com/mguthaus/status/1521906129126666243

04:57 ChipFlow's first video: https://www.youtube.com/watch?v=rVsOZE80c-k&t=1s

05:28 Ex-ex-ex-clusive MPW2 news

05:45 Maximo's great photo of MPW1 dies: https://twitter.com/maxiborga/status/1522372084671913985

Interview with Dinesh A - Riscduino
00:00 Intro00:45 about Dinesh02:39 Aim of Riscduino04:50 Aim to be pin compatible and with support of compiler and libraries06:10 Join the project - Dinesh is looking for help with analog, verification & embedded07:30 State of the Analog IP08:30 Tell us about your applications to MPW2, 3, 4 & 513:40 Great docs!14:02 Verification16:00 Timing analysis19:40 What do you think about OpenLane?24:10 Pin positions25:40 Clock domains

MPW1 lives, chip scans, epoxy, Efabless, CLEAR FPGA, Makercast & hackchat

January news update!MPW1 silicon & bringup, MPW4 submitted, MPW5 tapeout

Carlos' twitter space: https://twitter.com/carlosedp/status/1469355189891125255

Silicon compiler: https://www.siliconcompiler.com/

Amaranth: https://github.com/amaranth-lang/amaranth

MPW2 rerun: https://efabless.com/projects/585

MPW4 application: https://efabless.com/projects/596

Caravel restructure: https://github.com/efabless/caravel

SkullFET: https://twitter.com/UriShaked/status/1472258972505812992

Will's FPGA advent calendar: https://twitter.com/WillFlux/status/1465268154733637633

MPW3 App: SoC https://efabless.com/projects/481

SoC source: https://github.com/ChipFlow/caravel_user_project_mpw3.git

Amaranth: https://github.com/amaranth-lang/amaranth

In this interview we talk about Staf's recent tapeout, the flexcell standard cell generator and pdk master - a kind of API for pdks.Staf also gives his opinions on the state of the industry and whether we at an inflection point for open source silicon.