Zero to ASIC Course

Zero to ASIC Course

By Matt VennTechnologyEducationCourses
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Zero to ASIC Course episodes

  • Diego Hernando - analog circuits on the Google/Skywater/Efabless ASIC shuttle
    00:36? Diego's background
    01:30? choice of design and the new tools
    02:50? digital vs analog process
    09:05? op-amp specifications
    12:35? schematic in xschem
    13:40? open loop testbench
    14:26? spice setup
    15:37? simulation results
    17:44? layout in magic
    23:20? opamps placed in the user project wrapper of Caravel
    27:20? testing the ASIC
    Diego on linked.in: https://www.linkedin.com/in/diego-joa...?
    Diego's ASIC submission: https://github.com/diegohernando/cara...?
    xschem: https://xschem.sourceforge.io/stefan/...?

    30 min
  • Lakshmi S - Designing a PLL for the Google/Skywater/Efabless ASIC shuttle
    00:00? introduction
    01:04? worked under Kunal Ghosh as an intern: https://www.vlsisystemdesign.com/basi...?
    02:18? Questions from Niklas - time it takes, what's frustrating, fun?
    05:40? Are the tools ready for mixed signal designs - DRC violations in Caravel.
    07:20? Question from Pepijn - what would you need to change to alter the PLL?
    08:44? PLL overview
    10:00? Lakshmi's design: Frequency divider
    12:22? Phase frequency detector
    13:32? Charge pump
    14:37? Voltage controlled oscillator
    16:40? combined designs with Diego Hernando
    17:10? putting into the Caravel wrapper, adding space
    18:56? Question from Brady - why design an integrated loop filter
    20:01? Questions from Top - are there schematics? Process corners and ngspice convergence
    22:05? Question from Steven: post silicon testing
    Lakshmi on Linked.in: https://www.linkedin.com/in/lakshmis96/?
    Repo: https://github.com/lakshmi-sathi/avsd...
    25 min
  • Tim Edwards - what happens between ASIC submission and sending to Skywater?
    00:12 Tim Edwards introduction
    01:00 next steps after submission before files sent to Skywater
    02:00 infrastructure - getting all the latest from everyone's repositories
    03:05 size of the repos can be a problem
    03:41 revolutionary part of this run is that everything is Open Source down to the GDS
    04:51 Open Source PDK is what makes it possible to do this for eFabless
    05:12 Why didn't we submit the source rather than the final GDS?
    09:42 Got all the GDS2 files from the repos, what's the next step?
    10:00 3 scripts, 1st applies a user id
    13:04 2nd script does fill generation
    16:14 3rd script does compositing
    19:39 DRC count for Caravel
    23:00 lots of people have helped make this happen
    23:50 biggest project at eFabless
    24:00 When do you think the files will get sent to Skywater?
    Open Source VLSI tools: http://opencircuitdesign.com/
    eFabless: https://efabless.com/company
    31 min

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