Zero to ASIC Course

By Matt Venn

Interviews and news from the world of Open Source Silicon, ASICs and Semiconductors... more

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FAQs about Zero to ASIC Course:

How many episodes does Zero to ASIC Course have?

The podcast currently has 38 episodes available.

Zero to ASIC Course episodes:

March 23, 2021 Thomas Parry - Amateur satellite radio, Open Source vs Industry tools, beautiful analogue layout
00:00 Introducing Thomas Parry
00:36 Project is an amateur satellite transceiver
01:02 Thomas wanted a challenging project
01:17 His background
01:50 Working for SystematIC Design in Delft doing analogue chip design
02:29 Design split into 2 repositories, see links below
03:50 Day to day work with Cadence and MentorGraphics industry standard tools
04:25 Pay money to reduce risk - no one to shout at
05:42 Previous interviews with Diego & Lakshmi
06:04 His design process is similar
06:57 Using Klayout for layout
07:15 Using OpenLANE for a small part of the design
08:35 Still uses Magic for extraction of circuit
08:52 Nice structure in his repository
10:24 Overview of the structure of a transceiver
12:20 Difference of the visual appearance of digital vs analogue layout
12:46 Taking a look at the GDS
13:30 Control signals
13:46 Digital section - fractional N divider for the PLL
14:29 9x9 array charge pump output
15:30 VCO - do they always look like bathroom tiles?
15:55 4 inverting amplifiers arranged in a ring
16:35 Created MOSFETs with the generator in Magic, then exported into Klayout
17:08 8x4 blocks of output drivers
17:40 Compensation filter for the PLL is off-chip
18:50 Characterise bandgap in a thermal chamber
19:30 Bandgap references replicated 3 times for different measurement options
20:15 Lovely routing!
21:08 Drawn by hand…
21:14 Ruby & Python scripting for Klayout
21:45 Efabless are working to integrate Klayout more tightly into OpenLANE
22:54 Terminology corner: Corner!
24:04 Typical Typical
25:26 How to get the RF signals in and out of Caravel padring?
26:35 WLCSP
27:20 Currently IO cells are digital
27:44 First 8 pins can be switched to analogue, but not ideal for high frequency
28:16 Power amplification
28:58 What are the next steps? Complete the TX chain
30:20 How to get started with analogue design?
32:02 Python binding for spice: https://pypi.org/project/PySpice/
33:02 Books by Behzad Razavi are recommended.
Design repo: https://github.com/yrrapt/amsat_txrx_ic
Shuttle application repo: https://github.com/yrrapt/caravel_amsat_txrx_ic
Connect with Thomas here: https://www.linkedin.com/in/thomas-parry-60419468/
...more
35min
March 12, 2021 Sylvain "tnt" Munaut - testing USB peripherals on the Google/Skywater/Efabless ASIC shuttle
In this interview Sylvain talks about:
1:15? why he's excited about the shuttle
4:00? what is the design he's working on
8:00? expectation vs experience with the Open Source ASIC tools
8:57? a look at the final GDS files
14:20? differences between design for ASIC vs FPGA
16:38? tap cells
17:50? antenna rules
Sylvain's previous streams on the Skywater 130nm PDK:
https://www.youtube.com/watch?v=AT_Lc...?
https://www.youtube.com/watch?v=gRYBd...?
https://www.zerotoasic.com?
...more
21min
March 12, 2021 Vladimir Milovanović - putting a spectrometer on the Google/Skywater/Efabless ASIC shuttle
1:00? What made you excited about the shuttle?
2:22? The spectrometer design - radar signal processing
4:00? built in self test
4:18? in & output signals
6:00? design in Chisel
10:40? ASIC vs FPGA
11:30? showing the GDS
12:24? density of the design
13:30? contact details
https://github.com/milovanovic/spectr...?
https://www.zerotoasic.com/?
...more
15min
March 12, 2021 Arya Reais-Parsi - an FPGA for the Google/Skywater/Efabless ASIC shuttle
In this interview Arya Reais-Parsi talks about:
00:45? FPGA design is for a course
01:50? difference between other open FPGA fabrics
02:50? FPGAs as accelerators
04:27? their FPGA structure
06:30? how did they target ASIC?
09:27? GDS view of the FPGA structure
11:40? custom cells for FPGAs
14:40? making lab notes
16:00? how does actually taping something out change the feeling of the work?
17:10? how will this shuttle program changes things going forwards?
22:40? future of ASIC with more open tooling and access
24:30? toolchain for their FPGA: yosys & nextpnr
Their group's application is here:
https://github.com/ucb-cs250/caravel_...
...more
29min
March 12, 2021 Diego Hernando - analog circuits on the Google/Skywater/Efabless ASIC shuttle

00:36? Diego's background
01:30? choice of design and the new tools
02:50? digital vs analog process
09:05? op-amp specifications
12:35? schematic in xschem
13:40? open loop testbench
14:26? spice setup
15:37? simulation results
17:44? layout in magic
23:20? opamps placed in the user project wrapper of Caravel
27:20? testing the ASIC
Diego on linked.in: https://www.linkedin.com/in/diego-joa...?
Diego's ASIC submission: https://github.com/diegohernando/cara...?
xschem: https://xschem.sourceforge.io/stefan/...?

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30min
March 12, 2021 Lakshmi S - Designing a PLL for the Google/Skywater/Efabless ASIC shuttle
00:00? introduction
01:04? worked under Kunal Ghosh as an intern: https://www.vlsisystemdesign.com/basi...?
02:18? Questions from Niklas - time it takes, what's frustrating, fun?
05:40? Are the tools ready for mixed signal designs - DRC violations in Caravel.
07:20? Question from Pepijn - what would you need to change to alter the PLL?
08:44? PLL overview
10:00? Lakshmi's design: Frequency divider
12:22? Phase frequency detector
13:32? Charge pump
14:37? Voltage controlled oscillator
16:40? combined designs with Diego Hernando
17:10? putting into the Caravel wrapper, adding space
18:56? Question from Brady - why design an integrated loop filter
20:01? Questions from Top - are there schematics? Process corners and ngspice convergence
22:05? Question from Steven: post silicon testing
Lakshmi on Linked.in: https://www.linkedin.com/in/lakshmis96/?
Repo: https://github.com/lakshmi-sathi/avsd...
...more
25min
March 11, 2021 Anton Blanchard - Microwatt: a 64 bit OpenPOWER core, VHDL and OpenLANE.
https://github.com/antonblanchard/microwatt-caravel
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1h 1min
March 11, 2021 Tim Edwards - what happens between ASIC submission and sending to Skywater?
00:12 Tim Edwards introduction
01:00 next steps after submission before files sent to Skywater
02:00 infrastructure - getting all the latest from everyone's repositories
03:05 size of the repos can be a problem
03:41 revolutionary part of this run is that everything is Open Source down to the GDS
04:51 Open Source PDK is what makes it possible to do this for eFabless
05:12 Why didn't we submit the source rather than the final GDS?
09:42 Got all the GDS2 files from the repos, what's the next step?
10:00 3 scripts, 1st applies a user id
13:04 2nd script does fill generation
16:14 3rd script does compositing
19:39 DRC count for Caravel
23:00 lots of people have helped make this happen
23:50 biggest project at eFabless
24:00 When do you think the files will get sent to Skywater?
Open Source VLSI tools: http://opencircuitdesign.com/
eFabless: https://efabless.com/company
...more
31min

FAQs about Zero to ASIC Course:

How many episodes does Zero to ASIC Course have?

The podcast currently has 38 episodes available.