
Sign up to save your podcasts
Or
Today we’re talking about something that’s top-of-mind for a lot of you: closing the reliability gaps in increasingly complex analog and mixed-signal IC designs—and doing it earlier, faster, and more systematically.
As designs become more heterogeneous and integration of IP blocks more intricate, traditional simulation and ERC tools often aren’t enough. They’re reactive by nature, catching issues too late in the flow—when rework is costly, and design intent is harder to trace.
That’s why “shift-left” verification has become more than just a buzzword. It’s a strategic necessity. And today’s conversation is all about one of the tools helping to make that shift actionable: Siemens’ Insight Analyzer.
4.7
2727 ratings
Today we’re talking about something that’s top-of-mind for a lot of you: closing the reliability gaps in increasingly complex analog and mixed-signal IC designs—and doing it earlier, faster, and more systematically.
As designs become more heterogeneous and integration of IP blocks more intricate, traditional simulation and ERC tools often aren’t enough. They’re reactive by nature, catching issues too late in the flow—when rework is costly, and design intent is harder to trace.
That’s why “shift-left” verification has become more than just a buzzword. It’s a strategic necessity. And today’s conversation is all about one of the tools helping to make that shift actionable: Siemens’ Insight Analyzer.
1,645 Listeners
4,209 Listeners
26,327 Listeners
1,043 Listeners
505 Listeners
270 Listeners
2,528 Listeners
787 Listeners
425 Listeners
0 Listeners
453 Listeners
2,090 Listeners
418 Listeners
2,119 Listeners
464 Listeners